參數(shù)資料
型號(hào): MN89306
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
封裝: 18 X 18 MM, PLASTIC, LQFP-128
文件頁(yè)數(shù): 3/47頁(yè)
文件大?。?/td> 487K
代理商: MN89306
LSIs for Display
MN89306
11
s Pin Descriptions (continued)
3) RISC CPU Related Pins
Pin Name
I/O
Level
Function
CCLK
I
5 V TTL
CPU clock
CPU bus synchronization clock. A clock frequency of up to 33 MHz can be supported.
CS
#
I
5 V TTL
Chip select
The MN89306 will only accept access operations when CS# is low.
RD
#
I
5 V TTL
Read
Reads out MN89306 I/O registers or memory. This line is always used for word
access.
WE0
#
I
5 V TTL
Write low byte
Write signal for the CPU data bus low order byte, bits [7:0]. The MN89306 can be
set to operate as either a big endian or a little endian machine.
WE1
#
I
5 V TTL
Write high byte
Write signal for the CPU data bus high order byte, bits [15:8]. The MN89306 can
be set to operate as either a big endian or a little endian machine.
A[25 : 1]
I
5 V TTL
Address
CPU address lines.
D[15 : 0]
I/O
5 V TTL
Data
CPU data bus. The MN89306 can be set to operate as either a big endian or a little
endian machine.
RDY
#
O
5 V TTL
Ready/Wait
WAIT
#
The functions of this signal differs depending on the type of CPU selected.
RDY# control when MA[2:0]
= 101.
Reports to the CPU that processing has completed. This pin outputs a high level
when a wait is required to access the MN89306. When processing completes, the
MN89306 announces that fact by outputting a low level for 1 CCLK cycle.
Then, after outputting a high level for 1 CCLK cycle, it sets the output to the high-
impedance state.
WAIR# control when MA[2:0]
= 110.
Issues a wait request to the CPU. This pin outputs a low level only for the time
that the CPU must wait to access the MN89306. When processing completes, the
MN89306 informs the CPU that processing has completed by outputting a high
level for 1 CCLK cycle. Then, the output is set to the high-impedance state.
An external pull-up resistor is required, whichever function is used. Determine
the value of the pull-up resistor based on the range of the current capacities of this
pin and the other chips that share this pin.
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