參數(shù)資料
型號: MN89306
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
封裝: 18 X 18 MM, PLASTIC, LQFP-128
文件頁數(shù): 30/47頁
文件大?。?/td> 487K
代理商: MN89306
MN89306
LSIs for Display
36
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
16) SDRAM Read Timing (Burst length
= 2, CAS latency = 2)
MCLK
MCLKEN
MCS
#
RAS
#
CAS
#
WE
#
1
2
4
5
6
8
7
9 10
3
MA11
MA10
MA0 to MA9
HDQM
LDQM
MD
Bank0
Active
Bank0
Read with
auto precharge
7
6
11
12
13
14
Hi-Z
CA0
RA0
Q01
Q00
Q03
Q02
RA0
CA0
RA0
Don't care
Note) 1. T is one period of MCLK (the divided-by-2 PLL clock: 35 MHz to 65 MHz).
2. Values listed in the table apply when the external load capacitor is 20 pF. The output delay times will differ depending on
the external load capacitor.
3. The specification values are determined by referencing to 1.4 V.
No.
Descriptions
Min
Max
Unit
1
Clock period
T(at 65 MHz)
ns
2
MCLK high-level period
0.5T
2
ns
3
MCLK low-level period
0.5T
2
ns
4
MCLKEN hold time
3
ns
5
MCLKEN setup time
T
10
ns
6
Command setup time
T
10
ns
7
Command hold time
3
ns
8
TRCD control (controlled with bit 6 in XSR20)
2T
3T
ns
9
Address setup time
T
10
ns
10
Address hold time
3
ns
11
Access time from MCLK
13
ns
12
Data output hold time
3
ns
13
Data output off time
12
ns
14
NAPR control (controlled with bit 0 in XSR20)
T
2T
ns
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