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參數(shù)資料
| 型號： | MN89306 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128 |
| 封裝： | 18 X 18 MM, PLASTIC, LQFP-128 |
| 文件頁數(shù)： | 34/47頁 |
| 文件大?。?/td> | 487K |
| 代理商： | MN89306 |
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MN89306
LSIs for Display
4
s Block Functional Descriptions (continued)
7) Video FIFO/PSCONV
The video FIFO temporarily stores data read out of memory in fast page mode, converts that data to dot units
according to control signals from the CRT/LCD controller, and outputs that display data. In text mode, this circuit
calculates font addresses and issues access requests to the memory interface.
8) Attribute controller
The attribute controller processes data from the video FIFO according to the display mode and generates color data
for each dot. It also implements blinking, underlining, and enlargement in the horizontal direction.
9) Color palette
The color palette generates 4-bit data for each of the three colors red, green, and blue by accessing internal palette
memory according to data from the attribute controller.
10) Gray scale engine
The gray scale engine calculates a brightness level from a color signal and generates a monochrome level signal
when a monochrome STN LCD panel is used. This circuit supports two techniques for calculating the intensity: a
technique in which the G signal data is used directly as the intensity level and a technique in which the dot brightness
is calculated by simulating the NTSC luminance signal calculation. The generated monochrome level signal is output
as a gray-scale pattern optimal for that level. If a color STN is used, this circuit is used to generate gray-scale patterns
for each of the red, green, and blue data values from the color palette. These gray-scale patterns allow up to 16 levels
to be displayed by controlling the frame rate.
11) Half-frame control
When displaying on a DSTN panel, the post-level control data is stored for half the screen in video memory. Then,
a high refresh rate can be implemented at a low clock frequency by reading out data for half a frame from video
memory and sending that data to the LCD panel interface simultaneously with the data sent from the gray scale engine.
12) LCD panel interface
The LCD panel interface outputs the required synchronizing signals, data clock signals, and display data
appropriate for the type of LCD panel connected. This circuit supports both STN (including color and monochrome
units as well as SSTN and DSTN devices) and color TFT LCD panels. Note that if a DSTN panel is used, a data area
(with 3 bits per pixel) large enough to hold a half frame of data must be allocated in video memory.
13) BitBLT engine
The BitBLT engine provides high-speed data transfers either from the host to video memory or between areas in
video memory. During these data transfers, the BitBLT engine supports 16 operations that correspond to two-operand
(source and destination) raster operations. The monochrome source expansion function provided by this circuit can
also convert 1-bpp data to 4-, 8-, or 16-bpp data and transfer that data to the destination area. In addition, it also
provides a rectangular area fill function and a transparent function. These operations are supported only in the graphics
display modes, and operate in packed pixel mode (8 or 16 bits per pixel). The BitBLT engine can also be operated in
8-dot units in plane mode, and in 2-dot units in 4-bpp packed pixel mode.
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