參數(shù)資料
型號: MN89306
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
封裝: 18 X 18 MM, PLASTIC, LQFP-128
文件頁數(shù): 20/47頁
文件大?。?/td> 487K
代理商: MN89306
LSIs for Display
MN89306
27
No.
Descriptions
Min
Max
Unit
1
A[23:2], M/IO#, BE[3:0]#, and W/R# setup time
15
ns
2
A[23:2], M/IO#, BE[3:0]#, and W/R# hold time
0
ns
3
ADS# setup time
15
ns
4
ADS# hold time
3
ns
5
BS16# active delay time
28
ns
6
BS16# inactive delay time
28
ns
7
BS16# high-level output time
12
ns
8
CPU write data setup time
6
ns
9
CPU write data hold time
0
ns
10
CPU read data setup time
2CLK
40
ns
11
CPU read data output off delay time
5
28
ns
12
RDY# setup time
1CLK
25
ns
13
RDY# hold time
5
ns
14
RDY# high-level output time
0.5CLK
ns
15
CPU write wait time
1CLK
ns
16
CPU read wait time
2CLK
ns
17
LDEV# active delay time
28
ns
18
LDEV# inactive delay time
28
ns
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
7) 486CPU Local Bus Timing (continued)
Note) 1. : The wait time differs depending on the chip status.
2. CLK in the table refers to one clock period of CCLK.
3. Values listed in the table apply when the external load capacitor is 50 pF. The output delay times will differ depending on
the external load capacitor.
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