參數(shù)資料
型號(hào): MN89306
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
封裝: 18 X 18 MM, PLASTIC, LQFP-128
文件頁數(shù): 5/47頁
文件大小: 487K
代理商: MN89306
LSIs for Display
MN89306
13
4) Memory Access Related Pins
When EDO/Fast Page Mode DRAM is used.
Pin Name
I/O
Level
Function
MA[9 : 0]
I/O
CMOS
Display memory address
These pins are set to input mode by a reset, and the pins MA[2:0] are used to
decide the chip host type. The pins MA[9:3] are latched internally to the IC as the
expansion pin monitor register data.
16M DRAM
RAS address: MA[9:0], CAS address: MA[9:0]
MA[11:10]: Low-level output
4M DRAM
RAS address: MA[8:0], CAS address: MA[8:0]
MA[11:9]: Low-level output
MA10
I/O
CMOS
Display memory address10
After a reset, functions as the pin that selects whether SDRAM or EDO/fast page
mode memory is used. Do not pull up this line if EDO or fast page mode memory
is used.
RAS
#
O
Row address strobe
Row address latch strobe signal.
LCAS
#
O
Lower column address strobe for RAM
RAM low-order byte column address strobe signal.
UCAS
#
O
Upper column address strobe for RAM
RAM high-order byte column address strobe signal.
WE
#
O
Write enable
Data write signal
MD[15 : 0]
I/O
CMOS
Memory data bus
DRAM memory data.
s Pin Descriptions (continued)
3) RISC CPU Related Pins (continued)
RISC Interface (little endian)
WE1
# WE0# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
D15 D14 D13 D12 D11 D10
D9
D8
10
D7
D6
D5
D4
D3
D2
D1
D0
RISC Interface (big endian)
WE1
# WE0# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13 D12 D11 D10
D9
D8
0
1
D7
D6
D5
D4
D3
D2
D1
D0
10
D15 D14 D13 D12 D11 D10 D9 D8
The little endian or big endian state is set with bit 7 in the ENA register for I/O access, and with bit 0 in the XSRIE
register for memory access.
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