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參數(shù)資料
| 型號： | MN89306 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128 |
| 封裝： | 18 X 18 MM, PLASTIC, LQFP-128 |
| 文件頁數(shù)： | 23/47頁 |
| 文件大?。?/td> | 487K |
| 代理商： | MN89306 |
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LSIs for Display
MN89306
3
s Function Block Descriptions
1) Host interface
The host interface decodes the host bus addresses, generates the I/O and memory access enable signals, and transfers
required information for read and write operations to the chip internal registers and for memory read and write
operations. Data transfers are performed in 16-bit units for the ISA, 386, 486, and RISC buses.
Host bus type
Data bus width
ISA
16 bits
386SX, 486, VL
16 bits
RISC CPU
16 bits
Furthermore, since the MN89306 supports linear addressing, the CPU address calculation time can be reduced.
Thus memory accesses are faster than if memory were accessed using a VGA compatible address area.
Note) 1. ISA bus is a registered trademark of the (US) Industry Standards Architecture.
2. VL bus is a registered trademark of the (US) Video Electronics Standard Association.
3. VGA is a registered trademark of International Business Machines, Inc.
2) Write FIFO
The write FIFO provides a function that temporarily accumulates memory write requests from the CPU bus, and
thus significantly increases the speed with which the IC can handle CPU bus memory write requests. The FIFO can
hold 4 units of 16-bit data. This buffer compensates for the periods when the IC cannot accept CPU memory access
requests due to display refresh operations, thus significantly reducing the wait time associated with CPU memory
writes. Furthermore, in display modes that do not require VGA compatible processing, the graphics speed is increased
even further since data can be sent directly from the write FIFO to the memory access arbitrator.
3) Graphics controller
The graphics controller processes data from the write FIFO according to the mode specified by the current register
settings. According to the operating mode, this module performs data expansion processing on the data from the write
FIFO and then the resultant data is sent to the memory access arbitrator. Furthermore, according to the operating
mode, this module processes data read from memory and then sends the resultant data to the host interface.
4) Memory access arbitrator
The memory access arbitrator arbitrates memory access requests from the write FIFO, memory access requests from
the graphics controller, memory access requests from the BitBLT block, display data read requests from the LCD
controller, and memory access requests from the half frame controller. It then sends the memory access request,
address, and data to the memory interface.
5) Memory access interface
The memory access interface accesses memory according to request signals from the memory access arbitrator.
DRAM with fast page mode is used to read display data from memory as quickly as possible. The memory access
interface supports variable memory access timings to get the maximum speed possible from memory when fast DRAMs
are used. The memory access interface also outputs refresh signals according to the operating state of the chip.
6) CRT/LCD controller
This block generates the display address, display enable, and vertical and horizontal synchronizing signals required
for display. It also performs image enlargement in the vertical direction.
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