參數(shù)資料
型號(hào)： ML60851DTB
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類(lèi)： 總線(xiàn)控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁(yè)數(shù)： 68/84頁(yè)
文件大?。?/td> 394K
代理商： ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
69/83
(4) Receive packet ready interrupts (EP1, EP2)
These interrupts are generated when the respective EP has received an appropriate data packet from the USB
bus and the local MCU can read that data.
Operation
Source of operation
Description (conditions, responses, etc.)
Receive packet ready
interrupt generation
ML60851D
The receive packet ready bit of the corresponding EP
status register (EPnSTAT) is asserted during data
reception when the EOP of the data packet has been
received and the data has been stored without error in the
corresponding FIFO. The end of a packet is recognized
when an EOP has arrived in the cases of both full packets
and short packets.
An interrupt is generated at this time, if the corresponding
receive packet ready interrupt enable bit has been
asserted.
(EOP: End of packet)
End of receive packet ready
interrupt
Local MCU (firmware)
After the number of bytes in the receive FIFO data
(EPnFIFO) indicated by the corresponding receive byte
count register (EPnRXCNT) has been read, write a “1” into
the respective receive packet ready bit of the end point
packet ready register (PKTRDY). (This bit is reset when a
'1' is written in this bit.)
The following table outlines the relationship between ML60851D registers and packet ready interrupt generation
during EP1 or EP2 receive (host to device communication) operation.
INTENBL(D1/D2)*
EPnCON(D7)
Rx PKTRDY(D1/D2)*
INTSTAT(D1/D2)*
100
0
101
1
11
X
0
0X
X
0
* Use D1 bit when considering EP1 operation or use D2 bit when considering EP2 operation
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