參數(shù)資料
型號： ML60851DTB
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁數(shù)： 65/84頁
文件大?。?/td> 394K
代理商： ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
67/83
(2) EP0 Receive packet ready interrupt
This is used mainly during the reception of a data packet in a control write transfer.
Operation
Source of operation
Description (conditions, responses, etc.)
EP0 Receive packet ready
interrupt generation
ML60851D
The EP0 receive packet ready bit (D0 of PKTRDY) is
asserted during a control write transfer when the
processing has changed from the setup stage to the data
stage, and the ML60851D has detected EOP of the data
packet and has stored the data without error in the EP0
receive FIFO. The end of a packet is recognized when an
EOP has arrived in the cases of both full packets and short
packets.
An interrupt is generated at this time, if the EP0 receive
packet ready interrupt enable bit (D3 of INTENBL) has
been asserted.
(EOP: End of packet)
End of EP0 receive packet
ready interrupt
Local MCU (firmware)
In the case of EP0 reception, after the number of bytes of
the EP0 receive FIFO data indicated by the EP0 receive
byte count register (EP0RXCNT) has been read, write a '1'
in the EP0 receive packet ready bit (bit D0 of PKYRDY).
(This status is reset when a '1' is written in this bit.)
Note:
A short packet is a packet with a number of bytes less than the maximum packet size.
The following table outlines the relationship between ML60851D registers and EP0 receive packet ready interrupt
generation.
INTENBL(D3)
EP0 Rx PKTRDY(D0)
INTSTAT(D3)
100
111
0X0
X This symbol means that it does not matter whether the value is ‘1’ or ‘0’
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