參數(shù)資料
型號(hào): ML60851DTB
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁數(shù): 27/84頁
文件大?。?/td> 394K
代理商: ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
32/83
DMA Interval Register (DMAINTVL)
Read address
DEh
Write address
5Eh
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
000
0000
0
After a bus reset
The previous value is retained
Definition
Interval time
This register is used for specifying the interval of the single DMA transfer mode, that is, the interval from the
completion of the previous byte (or word) DMA transfer until DREQ is asserted again. The time per bit is 84 ns
(12 MHz, one period).
Interval time = (DREQ enable time) + 84 x n (ns)
See DMA timings (1), (2), (5), and (6) for details of the DREQ enable time.
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