參數(shù)資料
型號(hào)： ML60851DTB
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁(yè)數(shù)： 60/84頁(yè)
文件大?。?/td> 394K
代理商： ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
62/83
Application Interface
Signal
Type
Assertion
Description
D15:D8
I/O
—
Upper byte (MSB) of data bus. This data bus is used by applications to
access register files and FIFO data.
AD7:AD0
I/O
—
Lower byte (LSB) of data bus when ADSEL is LOW.
Address and lower byte of data bus are multiplexed when ADSEL is HIGH.
A7:A0
I
—
Address when ADSEL is LOW. This address signal is used by application to
access register files and FIFO data.
This signal is ignored (all lows or all highs) when ADSEL is HIGH.
CS
ILOW
Chip Select. When this signal is asserted LOW, the ML60851D is selected
and ready to read or write data.
RD
ILOW
Read Strobe. When this signal is asserted LOW, the Read instruction is
executed.
WR
ILOW
Write Strobe. When this signal is asserted LOW, the Write instruction is
executed.
INTR
O
LOW
(Note 1)
Interrupt Request. When this signal is asserted, the ML60851D makes an
interrupt request to the application.
DREQ
O
LOW
(Note 1)
DMA Request. This signal requests the Endpoint FIFO to make a DMA
transfer.
DACK
I
HIGH
(Note 1)
DMA Acknowledge Signal. This signal, when asserted, enables accessing
FIFOs, without address bus setting.
ALE
I
—
When ADSEL is HIGH, the address and
CS on AD7:AD0 is latched at the
trailing edge of this signal. This signal is ignored when ADSEL is LOW.
ADSEL
I
—
When ADSEL is LOW, the address is input on A7:A0 and data is input on
D15:D8 and AD7:AD0. When ADSEL is HIGH, the lower bytes (LSB) of
address and data are multiplexed on AD7:AD0.
RESET
ILOW
System Reset. When this signal is asserted LOW, the ML60851D is reset.
When the ML60851D is powered on, this signal must be asserted for 1
s or
more.
Note:
1. Initial value immediately after resetting. Its assertion can be changed by programming.
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