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參數(shù)資料
| 型號： | ML60851DTB |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 38/84頁 |
| 文件大?。?/td> | 394K |
| 代理商： | ML60851DTB |
FEDL60851D-01
1Semiconductor
ML60851D
42/83
End Point 2 Data Toggle Register (EP2TGL)
Read address
F5h
Write address
75h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
000
0000
0
After a bus reset
000
0000
0
Definition
000
0000
Data Sequence Toggle Bit: When initializing an EP after receiving a setup packet, write a “1” in this bit to reset
the toggle bit of the data packet and specify PID of DATA0 (this bit also becomes
“0”). Thereafter, the synchronous operation is made automatically based on the data
sequence toggling mechanism.
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it
will be invalid.
End Point 2 Payload Register (EP2PLD)
Read address
F6h
Write address
76h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
xx
xxxx
x
After a bus reset
0
xx
xxxx
x
Definition
0
Maximum packet size (R/W)
Maximum Packet Size:
The value of wMaxPacketSize of the end point descriptor selected by the
Set_Configuration request from the host computer should be written in this register by
the local MCU. The packet size of packets other than short packets is specified in
units of a byte. The value can be one of 40h (64 bytes), 20h (32 bytes), 10h (16 bytes),
and 08h (8 bytes). This register is used for EP2 reception. During data reception by
EP2, if a packet with more number of bytes than that specified here is received, the
receive packet ready bit is not asserted, and the stall bit is set during EOP and the stall
handshake is returned to the host computer.
Bit D7 is fixed at “0”, and even if a “1” is written, it will be invalid.
Data Sequence Toggle Bit
(R/Reset)
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