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參數(shù)資料
| 型號： | ML60851DTB |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 64/84頁 |
| 文件大?。?/td> | 394K |
| 代理商： | ML60851DTB |
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FEDL60851D-01
1Semiconductor
ML60851D
66/83
Interrupts
The ML60851D requests interrupts to the local MCU, etc., by asserting the -INTR pin. The interrupt causes are
the following:
(a)
Setup ready for the 8-byte setup data
(b)
EP0 receive packet ready
(c)
EP0 transmit packet ready
(d)
EP1 transmit/receive packet ready
(e)
EP2 transmit/receive packet ready
(f)
EP3 transmit packet ready
(g)
USB Bus reset
(h)
Suspend
Although there is only one
INTR pin, the local MCU can identify the contents of the interrupt by reading out the
interrupt status register. These interrupts can also be masked dynamically by making individual settings in the
interrupt enable register.
The causes of the interrupts, their setting and resetting conditions, and the responses to them are described below.
The functions of the setup ready bit and the packet ready bit can, in some situations, be different from those
described here because of some special automatic operations done by the ML60851D. Please see the descriptions
of the registers EP0STAT and PKTRDY for more details of such functions.
(1) Setup ready interrupt
Operation
Source of operation
Description (conditions, responses, etc.)
Setup ready
interrupt generation
ML60851D
The setup ready bit (D0 of EP0STAT) is asserted when the
8-byte setup control data is received normally and has
been stored in the set of setup registers.
An interrupt is generated at this time if D0 of INTENBL has
been asserted.
→ The firmware can now read the set of setup registers.
End of setup ready interrupt Local MCU (firmware)
After making the firmware read the 8-byte setup data, write
a “1” in bit D0 of EP0 status register (EP0STAT). This
causes the interrupt to be de-asserted.
The interrupt will not be de-asserted If a new 8-byte setup
data is received during this period. In this case, discard the
setup data that was being read at that time and read the
new 8-byte setup data.
The following table outlines the relationship between ML60851D registers and setup ready interrupt generation.
INTENBL(D0)
EP0STAT(D0)
INTSTAT(D0)
100
111
0X0
X This symbol means that it does not matter whether the value is ‘1’ or ‘0’
相關PDF資料 |
PDF描述 |
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| ML60852A | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ML60851E | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60851EGA | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60851ETB | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
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