參數(shù)資料
型號: ML60851DTB
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁數(shù): 40/84頁
文件大?。?/td> 394K
代理商: ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
44/83
End Point 3 Data Toggle Register (EP3TGL)
Read address
F9h
Write address
79h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
000
0000
0
After a bus reset
000
0000
0
Definition
000
0000
Data Sequence Toggle Bit: When initializing an EP, write a “1” in this bit to reset the toggle bit of the data packet
and specify PID of DATA0 (this bit also becomes “0”).
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.
End Point 3 Payload Register (EP3PLD)
Read address
FAh
Write address
7Ah
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
xx
xxxx
x
After a bus reset
0
xx
xxxx
x
Definition
0
7-Bit general purpose register
This register can be used for any purpose. It is possible to retain or refer to the value written in this register without
affecting the other operations of the ML60851D. The initial values of bits other than D7 are indeterminate. Bit D7
is fixed at “0” and even if a “1” is written in this bit, it will be invalid.
Data Sequence Toggle Bit
(R/Reset)
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