參數資料
型號: MFRC52201HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網絡
英文描述: Contactless reader IC
封裝: MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數: 65/92頁
文件大?。?/td> 691K
代理商: MFRC52201HN1
MFRC522_35
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
65 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
9.3.4.10
TestDAC1Reg register
Defines the test value for TestDAC1.
Table 135. TestDAC1Reg register (address 39h); reset value: xxh bit allocation
Bit
7
6
5
Symbol
reserved
Access
-
Table 136. TestDAC1Reg register bit descriptions
Bit
Symbol
7
reserved
6
reserved
5 to 0
TestDAC1[5:0] defines the test value for TestDAC1
output of DAC1 can be routed to AUX1 by setting value
AnalogSelAux1[3:0] to 0001b in the AnalogTestReg register
9.3.4.11
TestDAC2Reg register
Defines the test value for TestDAC2.
Table 137. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation
Bit
7
6
5
Symbol
reserved
Access
-
Table 138. TestDAC2Reg register bit descriptions
Bit
Symbol
7 to 6
reserved
5 to 0
TestDAC2[5:0] defines the test value for TestDAC2
output of DAC2 can be routed to AUX2 by setting value
AnalogSelAux2[3:0] to 0001b in the AnalogTestReg register
9.3.4.12
TestADCReg register
Shows the values of ADC I and Q channels.
Table 139. TestADCReg register (address 3Bh); reset value: xxh bit allocation
Bit
7
6
5
Symbol
ADC_I[3:0]
Access
R
Table 140. TestADCReg register bit descriptions
Bit
Symbol
7 to 4
ADC_I[3:0]
3 to 0
ADC_Q[3:0]
9.3.4.13
Reserved register 3Ch
Functionality reserved for production test.
4
3
2
1
0
TestDAC1[5:0]
R/W
Description
reserved for production tests
reserved for future use
4
3
2
1
0
TestDAC2[5:0]
R/W
Description
reserved for future use
4
3
2
ADC_Q[3:0]
R
1
0
Description
ADC I channel value
ADC Q channel value
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