參數(shù)資料
型號: MFRC52201HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 15/92頁
文件大小: 691K
代理商: MFRC52201HN1
MFRC522_35
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
15 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
Table 14.
7 (MSB)
1 = read
0 = write
8.1.4
I
2
C-bus interface
An I
2
C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus
interface to the host. The I
2
C-bus interface is implemented according to
NXP Semiconductors’
I
2
C-bus interface specification, rev. 2.1, January 2000
. The
interface can only act in Slave mode. Therefore the MFRC522 does not implement clock
generation or access arbitration.
The MFRC522 can act either as a slave receiver or slave transmitter in Standard mode,
Fast mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
MFRC522 has a 3-state output stage to perform the wired-AND function. Data on the
I
2
C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to
400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.
If the I
2
C-bus interface is selected, spike suppression is activated on lines SCL and SDA
as defined in the I
2
C-bus interface specification.
See
Table 155 on page 76
for timing requirements.
Address byte 0 register; address MOSI
6
5
reserved
address
4
3
2
1
0 (LSB)
Fig 11. I
2
C-bus interface
001aak590
MFRC522
SDA
SCL
I2C
EA
ADR_[5:0]
PULL-UP
NETWORK
CONFIGURATION
WIRING
PULL-UP
NETWORK
MICROCONTROLLER
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