參數(shù)資料
型號: MFRC52201HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡
英文描述: Contactless reader IC
封裝: MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 44/92頁
文件大?。?/td> 691K
代理商: MFRC52201HN1
MFRC522_35
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NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
44 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
9.3.1.14
BitFramingReg register
Adjustments for bit-oriented frames.
Table 47.
Bit
Symbol
Access
Table 48.
Bit
7
9.3.1.15
CollReg register
Defines the first bit-collision detected on the RF interface.
Table 49.
Bit
Symbol
Access
Table 50.
Bit
7
BitFramingReg register (address 0Dh); reset value: 00h bit allocation
7
6
5
4
StartSend
RxAlign[2:0]
W
R/W
3
2
1
0
reserved
-
TxLastBits[2:0]
R/W
BitFramingReg register bit descriptions
Symbol
Value Description
StartSend
1
starts the transmission of data
only valid in combination with the Transceive command
used for reception of bit-oriented frames: defines the bit
position for the first bit received to be stored in the FIFO buffer
example:
LSB of the received bit is stored at bit position 0, the second
received bit is stored at bit position 1
LSB of the received bit is stored at bit position 1, the second
received bit is stored at bit position 2
LSB of the received bit is stored at bit position 7, the second
received bit is stored in the next byte that follows at bit
position 0
These bits are only to be used for bitwise anticollision at
106 kBd, for all other modes they are set to 0
reserved for future use
used for transmission of bit oriented frames: defines the
number of bits of the last byte that will be transmitted
000b indicates that all bits of the last byte will be transmitted
6 to 4
RxAlign[2:0]
0
1
7
3
2 to 0
reserved
TxLastBits[2:0]
-
-
CollReg register (address 0Eh); reset value: xxh bit allocation
7
6
ValuesAfterColl
reserved
CollPosNotValid
R/W
-
5
4
3
2
1
0
CollPos[4:0]
R
R
CollReg register bit descriptions
Symbol
ValuesAfterColl
Value Description
0
all received bits will be cleared after a collision
only used during bitwise anticollision at 106 kBd,
otherwise it is set to logic 1
-
reserved for future use
1
no collision detected or the position of the collision is
out of the range of CollPos[4:0]
6
5
reserved
CollPosNotValid
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