參數(shù)資料
型號: MFRC52201HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡
英文描述: Contactless reader IC
封裝: MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 35/92頁
文件大小: 691K
代理商: MFRC52201HN1
MFRC522_35
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
35 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
21h
22h
23h
24h
25h
26h
27h
CRCResultReg
shows the MSB and LSB values of the CRC calculation
Table 87 on page 54
Table 89 on page 54
Table 91 on page 55
Table 93 on page 55
Table 95 on page 55
Table 97 on page 56
Table 99 on page 56
Reserved
ModWidthReg
Reserved
RFCfgReg
GsNReg
reserved for future use
controls the ModWidth setting
reserved for future use
configures the receiver gain
selects the conductance of the antenna driver pins TX1 and
TX2 for modulation
defines the conductance of the p-driver output during
periods of no modulation
defines the conductance of the p-driver output during
periods of modulation
defines settings for the internal timer
28h
CWGsPReg
Table 101 on page 57
29h
ModGsPReg
Table 103 on page 57
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Page 3: Test register
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch to 3Fh Reserved
TModeReg
TPrescalerReg
TReloadReg
Table 105 on page 57
Table 107 on page 58
Table 109 on page 59
Table 111 on page 59
Table 113 on page 60
Table 115 on page 60
defines the 16-bit timer reload value
TCounterValReg
shows the 16-bit timer value
Reserved
TestSel1Reg
TestSel2Reg
TestPinEnReg
TestPinValueReg
TestBusReg
AutoTestReg
VersionReg
AnalogTestReg
TestDAC1Reg
TestDAC2Reg
TestADCReg
reserved for future use
general test signal configuration
general test signal configuration and PRBS control
enables pin output driver on pins D1 to D7
defines the values for D1 to D7 when it is used as an I/O bus
Table 125 on page 62
shows the status of the internal test bus
controls the digital self test
shows the software version
controls the pins AUX1 and AUX2
defines the test value for TestDAC1
defines the test value for TestDAC2
shows the value of ADC I and Q channels
reserved for production tests
Table 117 on page 60
Table 119 on page 60
Table 121 on page 61
Table 123 on page 61
Table 127 on page 62
Table 129 on page 63
Table 131 on page 63
Table 133 on page 64
Table 135 on page 65
Table 137 on page 65
Table 139 on page 65
Table 141
to
Table 147
on page 66
Table 20.
Address
(hex)
MFRC522 register overview
…continued
Register name
Function
Refer to
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