參數(shù)資料
型號(hào)： MD2533-D16G-X-P/Y
廠商： SANDISK CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝： 12 X 18 MM, 1.40 MM HEIGHT, FBGA-115
文件頁(yè)數(shù)： 52/87頁(yè)
文件大?。?/td> 1675K
代理商： MD2533-D16G-X-P/Y
Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
56
92-DS-1205-10
cycle made to mDOC must observe the multiplexed mode protocol. See Section 10 for more
information about the related timing requirements.
Please refer to Section 2.3 for ballout and signal descriptions, and to Section 10 for timing
specifications for a multiplexed interface.
9.7
Implementing the Interrupt Mechanism
9.7.1
Hardware Configuration
To configure the hardware for working with the interrupt mechanism, the IRQ# ball should be
connected to a host interrupt input.
9.7.2
Software Configuration
IRQ# signal may be used by mDOC H3 to interrupt the host system, provided that device
interrupts are enabled. Interrupts can be enabled or disabled using the flHwConfig DOC Driver
API. For more information see the DOC Driver 1.0 Block Device (BD) Software Developer Kit
(SDK) Developer Guide. When asserted, the IRQ# signal will remain asserted until cleaned
(level only). This cleaning is performed automatically by the DOC Driver as part of the API
(read or write) completion.
mDOC H3 will interrupt the host system in the following cases:
Device is ready to receive a data block (excluding the first) during write operation.
When using DMA transfers:
On completion of block device operation to mDOC H3.
Device is ready to send a data block during a read operation.
9.8
DMA and Burst Operation
mDOC H3 enhances performance using various proprietary techniques among them are
Burst operation to read or write large chunks of data, providing a Burst speed.
DMA operation to release the CPU for other tasks in coordination with the platform’s
DMA controller. This is especially useful during the boot stage. Up to 128KB of data
can be transferred during a DMA operation.
9.8.1
DMA Operation
mDOC H3 provides a DMARQ# output that enables data transfer using the host DMA
controller. During DMA operation, the DMARQ# output is used to notify the host DMA
controller that data is ready to be read or written. mDOC H3 protocol enables such data transfer
up to the maximal size of 128KB per read or write operation.
The DMARQ# output sensitivity is selected by setting the EDGE bit in the DMA Control
register:
1. Edge DMARQ# output pulses to indicate to the DMA controller that a data is ready to be
transferred. The EDGE bit is set to 1 for this mode. The amount of data that will be
transferred corresponds to data block size.
相關(guān)PDF資料
PDF描述
MD2534-D1G-X-P FLASH MEMORY DRIVE CONTROLLER, PBGA115
MD2533-D8G-X-P FLASH MEMORY DRIVE CONTROLLER, PBGA115
SDED5-008G-NCY FLASH MEMORY DRIVE CONTROLLER, PBGA115
MD80C154-12/883 8-BIT, 12 MHz, MICROCONTROLLER, CDIP40
MD80C154-16P883D 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40
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