參數(shù)資料
型號(hào)： MCRF360
廠商： Microchip Technology Inc.
英文描述： CONNECTOR
中文描述： 連接器
文件頁(yè)數(shù)： 8/23頁(yè)
文件大小： 568K
代理商： MCRF360
MCRF355/360
DS21287F-page 8
2002 Microchip Technology Inc.
2.2
Controller Logic Section
2.2.1
CLOCK PULSE GENERATOR
This circuit generates a clock pulse (CLK). The clock
pulse is generated by an on-board time-base oscillator.
The clock pulse is used for baud rate timing, data
modulation rate, etc.
2.2.2
MODULATION LOGIC
This logic acts upon the serial data (154 bits) being
read from the memory array. The data is then encoded
into Manchester format. The encoded data is then fed
to the modulation transistor in the Analog Front-End
section. The Manchester code waveform is shown in
Figure 2-2.
2.2.3
SLEEP TIMER
This circuit generates a SLEEP time (100 ms ± 50%)
for the anti-collision feature. During this SLEEP time
(T
OFF
), the modulation transistor remains in a turned-
on condition (cloaked) which detunes the LC resonant
circuit.
2.2.4
READ/WRITE LOGIC
This logic controls the reading and programming of the
memory array.
FIGURE 2-2:
CODE WAVEFORMS
Data
NRZ-L
(Reference only)
BIPHASE-L
(Manchester)
SIGNAL
WAVEFORM
DESCRIPTION
Digital Data
Non-Return to Zero – Level
“1” is represented by logic high level.
“0” is represented by logic low level.
Biphase – Level (Split Phase)
A level change occurs at middle of
every bit clock period.
“1” is represented by a high to low
level change at midclock.
“0” is represented by a low to high
level change at midclock.
CLK
Internal Clock Signal
1
0
1
1
0
0
0
1
1
0
1
0
Note:
The CLK and NRZ-L signals are shown for reference only. BIPHASE-L (Manchester) is the device output.
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