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參數(shù)資料
| 型號： | MCM20027IBMN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 圖像傳感器 |
| 英文描述： | Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
| 中文描述： | IMAGE SENSOR-CMOS, 10fps, 0.20-2.80V, SQUARE, SURFACE MOUNT |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 46/74頁 |
| 文件大小： | 973K |
| 代理商： | MCM20027IBMN |
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MOTOROLA
Revision 8.0 - 28 November 2001 : MCM20027
46
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
13.3 Offset Calibration Block
Offset adjustments for the MCM20027 are done in sep-
arate sections of the ASP to facilitate FPN removal and
final image black level set.
The
Column DOVA DC Register; Table 26
, is used to
set the initial offset of the pixel output in a range that will
facilitate per-column offset data generation for varying
operational conditions. In most operational scenarios,
this register can be left in its default state of 00
h
. This is
a pre-image processing gain in comparison to the
Glo-
bal DOVA Register
which is a post image processing
chain gain (pre A2D gain).
This register can also be used to apply a global offset
adjust. In this case, the user must take into account the
Color Gain and Global Gain registers to determine the
resulting offset at the output.
The
Mod64 Column Offset registers; Table 27
are used
in conjunction with the
Column DOVA DC Register; Ta-
ble 26
to reduce/eliminate fixed pattern noise (FPN).
There are 64 registers that can be programmed with in-
dividual offset values. They will be applied to all the col-
umns on a single image frame on a Modular 64
basis.i.e. Register 80
h
Column offset will be applied to
Column 0 , Register 81
h
Column offset will be applied to
Column 1, Register BF
h
Column offset will be applied to
Column 63, Register 80
h
Column offset will be applied
to Column 0..etc..
7 - 3
Unused
Unused
xxxx
2
White Bal-
ance Gain
Mode
0
b
= Raw gain mode
1
b
= Linear gain mode
0
b
1 - 0
Exposure
Gain Mode
00
b
= Raw gain mode
01
b
= Linear gain mode
1x
b
= Linear 2 gain mode
00b
Address
22
h
PGA Gain Mode
Default
00
h
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
x
wbm
egm[1]
egm[0]
Table 25. PGA Gain Mode
Address
20
h
Column DOVA DC
Default
00
h
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
cdd[5]
cdd[4]
cdd[3]
cdd[2]
cdd[1]
cdd[0]
Bit
Number
Function
Description
Reset
State
7 - 6
Unused
Unused
xx
5
Sign
0
b
= Positive Offset
1
b
= Negative Offset
0
b
4 - 0
Column
DC Offset
Offset = 2.6 * cdd
d
(64 steps @ 2.6mV /Step)
00000
b
Table 26. Column DOVA DC Register
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