參數(shù)資料
型號(hào)： MCM20027IBMN
廠商： MOTOROLA INC
元件分類： 圖像傳感器
英文描述： Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control
中文描述： IMAGE SENSOR-CMOS, 10fps, 0.20-2.80V, SQUARE, SURFACE MOUNT
封裝： CERAMIC, LCC-48
文件頁(yè)數(shù)： 26/74頁(yè)
文件大?。?/td> 973K
代理商： MCM20027IBMN
MOTOROLA
Revision 8.0 - 28 November 2001 : MCM20027
26
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
10.0 I
2
C Serial Interface
The I
2
C is an industry standard which is also compatible
with the Motorola bus (called M-Bus) that is available on
many microprocessor products. The I
2
C contains a se-
rial two-wire half-duplex interface that features bidirec-
tional operation, master or slave modes, and multi-
master environment support. The clock frequency on
the system is governed by the slowest device on the
board. The SDATA and SCLK are the bidirectional data
and clock pins, respectively. These pins are open drain
and will require a pull-up resistor to VDD of 1.5 k
to 10
k
(see
page 66
).
The I
2
C is used to write the required user system data
into the Program Control Registers in the MCM20027.
The I
2
C bus can also read the data in the Program Con-
trol Register for verification or test considerations. The
MCM20027 is a slave only device that supports a max-
imum clock rate (SCLK) of 100 kHz while reading or
writing only one register address per I2C start/stop cy-
cle. The following sections will be limited to the methods
for writing and reading data into the MCM20027 regis-
ter.
For a complete reference to I
2
C, see “The I
2
C Bus from
Theory to Practice” by Dominique Paret and Carll-
Fenger, published by John Wiley & Sons, ISBN
0471962686.
10.1 MCM20027 I2C Bus Protocol
The MCM20027 uses the I2C bus to write or read one
register byte per start/stop I2C cycle as shown in
Figure
17
and
Figure 18
. These figures will be used to describe
the various parts of the I2C protocol communications as
it applies to the MCM20027.
MCM20027 I2C bus communication is basically com-
posed of following parts: START signal, MCM20027
slave address (0110011
b
) transmission followed by a R/
W bit, an acknowledgment signal from the slave, 8 bit
data transfer followed by another acknowledgment sig-
nal, STOP signal, Repeated START signal, and clock
synchronization.
10.2 START Signal
When the bus is free, i.e. no master device is engaging
the bus (both SCLK and SDATA lines are at logical “1”),
a master may initiate communication by sending a
START signal. As shown in
Figure 17
, a START signal
is defined as a high-to-low transition of SDATA while
SCLK is high. This signal denotes the beginning of a
new data transfer and wakes up all the slaves on the
bus.
10.3 Slave Address Transmission
The first byte of a data transfer, immediately after the
START signal, is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/
W bit. The seven-bit address for the MCM20027, start-
ing with the MSB (AD7) is 0110011
b
. The transmitted
calling address on the SDATA line may only be
changed while SCLK is low as shown in
Figure 17
. The
data on the SDATA line is valid on the High to Low sig-
nal transition on the SCLK line. The R/W bit following
the 7-bit tells the slave the desired direction of data
transfer:
1 = Read transfer, the slave transitions to a slave
transmitter and sends the data to the master
0 = Write transfer, the master transmits data to the
slave
10.4 Acknowledgment
Only the slave with a calling address that matches the
one transmitted by the master will respond by sending
back an acknowledge bit. This is done by pulling the
SDATA line low at the 9th clock (see
Figure 17
). If a
transmitted slave address is acknowledged, successful
slave addressing is said to have been achieved. No two
slaves in the system may have the same address. The
MCM20027 is configured to be a slave only.
10.5 Data Transfer
Once successful slave addressing is achieved, data
transfer can proceed between the master and the se-
lected slave in a direction specified by the R/W bit sent
by the calling master. Note that for the first byte after a
start signal (in
Figure 17
and
Figure 18
), the R/W bit is
always a “0” designating a write transfer. This is re-
quired since the next data transfer will contain the reg-
ister address to be read or written.
All transfers that come after a calling address cycle are
referred to as data transfers, even if they carry sub-ad-
dress information for the slave device.
Each data byte is 8 bits long. Data may be changed only
while SCLK is low and must be held stable while SCLK
is high as shown in
Figure 17
. There is one clock pulse
on SCLK for each data bit, the MSB being transferred
first.
Each data byte has to be followed by an acknowledge
bit, which is signalled from the receiving device by pull-
ing the SDATA low at the ninth clock. So one complete
data byte transfer needs nine clock pulses. If the slave
receiver does not acknowledge the master, the SDATA
line must be left high by the slave. The master can then
generate a stop signal to abort the data transfer or a
start signal (repeated start) to commence a new calling.
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