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參數(shù)資料
| 型號： | MCM20027IBMN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 圖像傳感器 |
| 英文描述： | Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
| 中文描述： | IMAGE SENSOR-CMOS, 10fps, 0.20-2.80V, SQUARE, SURFACE MOUNT |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 40/74頁 |
| 文件大?。?/td> | 973K |
| 代理商： | MCM20027IBMN |
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MOTOROLA
Revision 8.0 - 28 November 2001 : MCM20027
40
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
these values, the user should keep the voltage range
centered around 1.25V.
13.1.3 Analog Control Registers
The Analog Register Block also contains a
Power Con-
figuration Register; Table 19
, and a
Reset Control Reg-
ister; Table 20
.
The
Power Configuration Register
controls the internal
analog functionality that directly effect power consump-
tion of the device. An external precision resistor pin is
available on the MCM20027 that may be used to more
accurately regulate the internal current sources. This
serves to minimize variations in power consumption that
are caused by variations in internal resistor values as
well as offer a method to reduce the power consumption
of the device. The default for this control uses the inter-
nally provided resistor which is nominally 12.5k
. This
feature is enabled by setting the
res
bit of the
Power
Configuration Register
and placing a resistor between
the pin; EXTRES, and ground.
Figure 11
depicts the
power savings that can be achieved with an external re-
sistor at a specific clock rate. Power is further reduced
at lower clock rates.
The
pbg
bit of the
Power Configuration Register; Table
19
, is used to enable/disable the “Programmable Bias
Generator”. When this bit is enabled, the user can vary
the power consumption of the White Balance PGA
(PGAWB), Exposure gain PGA A (PGAEXPa), Expo-
sure gain PGA B (PGEXPb), Frame Rate Clamp (FRC),
Column Offset DOVA (COL_DOVA), Global offset
DOVA (DOVE) and/or the Analog to Digital converter
(A2D) between half an full current (power) consumption.
in the
Programable Bias Generator Control register; Ta-
ble 22
.
When this bit is disabled, it will use the power config-
ured by the internal or external resistor (bit 3).
Address
0A
h
Voltage Reference “Negative” Code
Default
76
h
msb (7)
6
5
4
3
2
1
lsb (0)
nrv[7]
nrv[6]
nrv[5]
nrv[4]
nrv[3]
nrv[2]
nrv[1]
nrv[0]
Bit
Number
Function
Description
Reset
State
7 - 0
Reference
Voltage = 0.0 + (5mV * nrc
d
)
01110110
b
(0.6V)
Table 17. Negative Voltage Reference Code Register
Address
0B
h
Voltage Reference “Positive” Code
Default
80
h
msb (7)
6
5
4
3
2
1
lsb (0)
prv[7]
prv[6]
prv[5]
prv[4]
prv[3]
prv[2]
prv[1]
prv[0]
Bit
Number
Function
Description
Reset
State
7 - 0
Reference
Voltage = 2.5 - (5mV * prv
d
)
10000000
b
(1.9V)
Table 18. Positive Voltage Reference Code Register
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