參數(shù)資料
型號： MCM20027IBMN
廠商： MOTOROLA INC
元件分類： 圖像傳感器
英文描述： Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control
中文描述： IMAGE SENSOR-CMOS, 10fps, 0.20-2.80V, SQUARE, SURFACE MOUNT
封裝： CERAMIC, LCC-48
文件頁數(shù)： 22/74頁
文件大?。?/td> 973K
代理商： MCM20027IBMN
MOTOROLA
Revision 8.0 - 28 November 2001 : MCM20027
22
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
9.0 Sensor Output/Input Signals
9.1 Start Of Data Capture (SYNC)
This signal is utilized by the sensor to indicate the start
of integration (data capture) in Single Frame Rolling
Shutter capture mode (SFRS). For more info refer to
Figure 15, on page 22
,
Figure 8, on page 12
and
Figure
16, on page 24
. This signal can be generated internally
by the sensor or be driven via Pin # 46 of the sensor
(see
Figure 20, on page 67
). To set whether the signal
is generated internally or externally, as well as other
settings to this signal, refer to
Sync and Strobe Control
register, (Table 31), on page 50
.
9.2 Start Of Row Readout (SOF)
This signal triggers/indicates the start of Row Readout
of the frame. This signal is an Output and can be read
via Pin # 48 of the sensor (see
Figure 20, on page 67
).
The SOF signal delay as well as its length can be set by
the user via
SOF Delay Register, (Table 46), on page
57
and
SOF & VCLK Signal Length Control Register,
(Table 48), on page 57
. For timing diagrams depicting
the use of the SOF signal refer to
Figure 15, on
page 22
,
Figure 6, on page 11
,
Figure 7, on page 12
,
Figure 8, on page 12
and
Figure 16, on page 24
.
9.3 Horizontal Data SYNC (VCLK)
This signal triggers the Readout of the sequential rows
of the frame. This signal is an Output and can be read
via Pin # 44 of the sensor (see
Figure 20, on page 67
).
The VCLK signal delay in relation to SOF, as well as its
length can be set by the user via
VCLK Delay Register,
(Table 47), on page 57
and
SOF & VCLK Signal Length
Control Register, (Table 48), on page 57
. For timing di-
agrams depicting the use of the VCLK signal refer to
Fig-
ure 15, on page 22
,
Figure 6, on page 11
,
Figure 7, on
page 12
,
Figure 8, on page 12
and
Figure 16, on
page 24
.
9.4 Data Valid (HCLK)
This signal triggers/indicates a single active pixel data
has been readout (eg Column 5 of Row 10 data has
been read out). This signal is an Output and can be
read via Pin # 45 of the sensor (see
Figure 20, on
page 67
). The HCLK signal delay can be set by the user
via
HCLK Delay Register, (Table 52), on page 60
. For
timing diagrams depicting the use of the HCLK signal
refer to
Figure 15, on page 22
,
Figure 6, on page 11
,
Figure 7, on page 12
,and
Figure 8, on page 12
.
Figure 15.
Pixel Data Bus Iinterface Timing Specifications (see Table Below)
MCLK
SYNC
t
hsync
t
susync
t
dsof
t
dvclk
SOF
VCLK
t
drhclk
HCLK
t
dadc
ADC[9:0]
t
dfhclk
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