參數(shù)資料
型號(hào): MCF5471ZP200
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 89/96頁
文件大?。?/td> 2003K
代理商: MCF5471ZP200
MOTOROLA
MCF547x Integrated Microprocessor Hardware Specifications
9
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MCF547x Family Features
1.4.5
PLL and Chip Clocking Options
MCF547x products contain an on-chip PLL capable of accepting input frequencies from 30–66.66 MHz.
Table 2 contains the frequencies of the system buses for the members of the MCF547x family under various
core/SDRAM/PCI/Flexbus clocking options.
1.4.6
Communications I/O Subsystem
1.4.6.1
DMA Controller
The communications subsystem contains an intelligent DMA unit that provides front line interrupt control
and data movement interface via a separate peripheral bus to the on-chip peripheral functions, leaving the
processor core free to handle higher level activities. This concurrent operation enables a significant boost in
overall system performance.
The communications subsystem can support up to 16 simultaneously enabled DMA tasks, with support for
up to 2 external DMA requests. It uses internal buffers to prefetch reads and post writes such that bursting
is used whenever possible. This optimizes both internal and external bus activity. The following
communications and computer control peripheral functions are integrated and controlled by the
communications subsystem:
Up to two 10/100 Mbps fast Ethernet controllers (FECs)
Optional universal serial bus (USB) version 2.0 device controller
Up to four programmable serial controllers (PSCs)
I2C peripheral interface
DMA serial peripheral interface (DSPI)
1.4.6.2
10/100 Fast Ethernet Controller (FEC)
The FEC supports the following standard MAC/PHY interfaces: 10/100 Mbps IEEE 802.3 MII, and
10Mbps 7-wire interface. The controller is full duplex, supports a programmable maximum frame length
and retransmission from the transmit FIFO following a collision.
Support for different Ethernet physical interfaces:
— 100 Mbps IEEE 802.3 MII
— 10 Mbps IEEE 802.3 MII
— 10 Mbps 7-wire interface
IEEE 802.3 full-duplex flow control.
Support for full-duplex operation (200 Mbps throughput) with a minimum system clock frequency
of 50 MHz.
Table 2. MCF54
7x Family Clocking Options
Core
(MHz)
Internal XLB and SDRAM
Bus Frequency
(MHz)
CLKIN—PCI and FlexBus
Frequency
(MHz)
Clock Ratio
240.0–266.66
120–133.33
30.0–33.3
1:4
120.0–266.66
60.0–133.33
30.0–66.66
1:2
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