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| 型號： | MCF5471ZP200 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388 |
| 文件頁數(shù)： | 36/96頁 |
| 文件大小： | 2003K |
| 代理商： | MCF5471ZP200 |
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MOTOROLA
MCF547x Integrated Microprocessor Hardware Specifications
41
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.14.1 Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used as the timing
reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the same frequency as the core
processor and cache memory. The frequency is 2x the internal system clock.
1.5.1.14.2 Processor Status Debug Data (PSTDDATA[7:0])
Processor status data outputs indicate both processor status and captured address and data values. They
operate at half the processor’s frequency, using PSTCLK. Given that real-time trace information appears as
a sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may
appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant.
1.5.1.14.3 Development Serial Clock/Test Reset (DSCLK/TRST)
If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to
the debug module. The maximum DSCLK frequency is 1/5 CLKIN.
If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG controller to the test
logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this occurs,
JTAG logic is benign and does not interfere with normal MCF547x functionality.
Although TRST is asynchronous, Motorola recommends that it makes an asserted-to-negated transition
only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to a
logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to EVDD. Tying TRST
to ground places the JTAG controller in test logic reset state immediately. Tying it to EVDD causes the JTAG
controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.
1.5.1.14.4 Breakpoint/Test Mode Select (BKPT/TMS)
If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug mode.
If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test
operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising edge
of TCK determine whether the JTAG controller holds its current state or advances to the next state. This
directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up resistor so
that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be tied to VDD.
1.5.1.14.5 Development Serial Input/Test Data Input (DSI/TDI)
If MTMOD0 is low, DSI is selected. DSI provides the single-bit communication for debug module
commands.
If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG
boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG controller
state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge. TDI has
an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it should be
tied to EVDD.
1.5.1.14.6 Development Serial Output/Test Data Output (DSO/TDO)
If MTMOD0 is low, DSO is selected. DSO provides single-bit communication for debug module responses.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5472 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics |
| MCF5472EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x ColdFire Microprocessor |
| MCF5472VR200 | 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5472ZP200 | 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5473 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics |
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