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| 型號(hào)： | MCF5471ZP200 |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388 |
| 文件頁(yè)數(shù)： | 71/96頁(yè) |
| 文件大小： | 2003K |
| 代理商： | MCF5471ZP200 |
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MOTOROLA
MCF547x Integrated Microprocessor Hardware Specifications
73
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
A.4.1
Power Up Sequence
If EVDD/SD VDD are powered up with the IVDD at 0V, then the sense circuits in the I/O pads will cause all
pad output drivers connected to the EVDD/SD VDD to be in a high impedance state. There is no limit on how
long after EVDD/SD VDD powers up before IVDD must power up. IVDD should not lead the EVDD, SD VDD
or PLL VDD by more than 0.4V during power ramp up or there will be high current in the internal ESD
protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid
turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 microsecond or slower rise time for all supplies.
2. IVDD/PLL VDD and EVDD/SD VDD should track up to 0.9V and then separate for the completion
of ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is
to use a low drop-out voltage regulator.
A.4.2
Power Down Sequence
If IVDDPLL VDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to
be in a high impedance state. There is no limit on how long after IVDD and PLL VDD power down before
EVDD or SD VDD must power down. IVDD should not lag EVDD, SD VDD, or PLL VDD going low by more
than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There
are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IVDD/PLL VDD to 0V.
2. Drop EVDD/SD VDD supplies.
A.5
Output Driver Capability and Loading
Table 24 lists values for drive capability and output loading.
Table 24. I/O Driver Capability
Signal
Drive
Capability
Output
Load (CL)
SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0],
SDWE, SDBA[1:0]
24 mA
15 pF
SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0],
SDCLK[1:0], SDCKE)
24 mA
15 pF
SDRAMC chip selects (SDCS[3:0])
24 mA
15 pF
FlexBus (AD[31:0], FBCS[5:0], TS, R/W, BE/BWE[3:0], OE)
16 mA
20 pF
FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXER
8 mA
15 pF
Timer (TOUT[3:0])
8 mA
50 pF
DACK[1:0]
8 mA
30 pF
PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC,
8 mA
30 pF
DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS)
24 mA
50 pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5472 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics |
| MCF5472EC | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MCF547x ColdFire Microprocessor |
| MCF5472VR200 | 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5472ZP200 | 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5473 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics |
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