參數(shù)資料
型號(hào)： MCF5471ZP200
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù)： 77/96頁(yè)
文件大?。?/td> 2003K
代理商： MCF5471ZP200
MOTOROLA
MCF547x Integrated Microprocessor Hardware Specifications
79
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
Table 29. SDR Timing Specifications
Symbol
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
83
133
Mhz
1
The frequency of operation is either 2x or 4x the CLKIN frequency of operation. MCF547X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock
operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF547X Specification
for more information on setting the SDRAM clock rate.
SD1
Clock Period (tCK)7.52
12
ns
2
SDCLK is one SDRAM clock in (ns).
SD2
Clock Skew (tSK)TBD
SD3
Pulse Width High (tCKH)
0.45
0.55
SDCLK
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD4
Pulse Width Low (tCKL)
0.45
0.55
SDCLK
4
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD5
Address, CKE, CAS, RAS, WE, BA, CS - Output Valid
(tCMV)
0.5*SDCLK
+ 1.0ns
ns
SD6
Address, CKE, CAS, RAS, WE, BA, CS - Output Hold
(tCMH)
2.0
ns
SD7
SDRDQS Output Valid (tDQSOV)
Self timed
ns
5
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for
each data beat.
SD8
SDDQS[3:0] input setup relative to SDCLK (tDQSIS)0.25*SDCL
K
0.40*SDCL
K
ns
6
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only.
Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will
occur for each data beat.
SD9
SDDQS[3:0] input hold relative to SDCLK (tDQSIH)
Does not apply. 0.5 SDCLK fixed
width.
7
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling
edge does not affect the memory controller.
SD10
Data Input Setup relative to SDCLK (reference only) (tDIS)0.25*SDCL
K
ns
8
Since a read cycle in SDR mode still uses the DQS circuit within MCF547X, it is most critical that the data valid
window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR
reads. The input setup spec is just provided as guidance.
SD11
Data Input Hold relative to SDCLK (reference only) (tDIH)1.0
ns
SD12
Data and Data Mask Output Valid (tDV)
0.75*SDCL
K +0.500ns
ns
SD13
Data and Data Mask Output Hold (tDH)1.5
ns
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MCF5472VR200 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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