參數(shù)資料
型號(hào)： MCF5471ZP200
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù)： 30/96頁(yè)
文件大小： 2003K
代理商： MCF5471ZP200
36
MCF547x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.6.6
AD[1:0]—Port Size Configuration (PSCONFIG)
The default port size value of the boot FBCS0 is determined by the logic levels driven on AD[1:0] at the
rising edge of RSTI, which are reflected as the reset value of CSCR0[PS]. Table 11 shows how the logic
levels of AD[1:0] correspond to the FBCS0 port size at reset.
1.5.1.7
Ethernet Module Signals
The following signals are used by the Ethernet module for data and clock signals.
1.5.1.7.1
Management Data (E0MDIO, E1MDIO)
The bidirectional EMDIO signals transfer control information between the external PHY and the
media-access controller. Data is synchronous to EMDC and applies to MII mode operation. This signal is
an input after reset. When the FEC operates in 10 Mbps 7-wire interface mode, this signal should be
connected to VSS.
1.5.1.7.2
Management Data Clock (E0MDC, E1MDC)
EMDC is an output clock which provides a timing reference to the PHY for data transfers on the EMDIO
signal and applies to MII mode operation.
1.5.1.7.3
Transmit Clock (E0TXCLK, E1TXCLK)
This is an input clock which provides a timing reference for ETXEN, ETXD[3:0] and ETXER.
1.5.1.7.4
Transmit Enable (E0TXEN, E1TXEN)
The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the first ETXCLK following the final
nibble of the frame.
Table 10. AD2/AA_CONFIG Selection of FBCS0 Automatic Acknowledge
AD2
Boot FBCS0 AA Configuration at Reset
0
Disabled
1
Enabled with 63 wait states
Table 11. AD[1:0]/PSCONFIG[1:0] Selection of FBCS0 Port Size
AD[1:0]
Boot FBCS0 Port Size
00
32-bit port
01
8-bit port
1X
16-bit port
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