參數(shù)資料
型號(hào): MCF5471ZP200
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù): 35/96頁(yè)
文件大?。?/td> 2003K
代理商: MCF5471ZP200
40
MCF547x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.11.3 Clear-to-Send (PSCnCTS/PSCBCLK)
These signals either operate as the clear to send input signals in UART mode or the bit clock input signals
in modem modes and IrDA modes. In MIR and FIR mode, the frequency is a multiple of the input bit clock
frequency, and the bit clock frequency should be within +/-0.1% and +/-0.01% of the ideal one, respectively.
1.5.1.11.4 Request to Send (PSCnRTS/PSCFSYNC)
The PSCnRTS signals act as transmitter request to send (RTS) outputs in UART mode, the frame sync input
in modem8 and modem16 modes or the RTS output (which acts as frame sync) in AC97 modem mode.
1.5.1.12 DMA Controller Module Signals
The DMA controller module uses the signals in the following subsections to provide external requests for
either a source or destination.
1.5.1.12.1 DMA Request (DREQ[1:0])
These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and
memory by either channel 0 or 1 of the on-chip DMA module.
1.5.1.12.2 DMA Acknowledge (DACK[1:0])
These outputs are asserted to acknowledge that a DMA request has been recognized.
1.5.1.13 Timer Module Signals
The signals in the following sections are external interfaces to the four general-purpose MCF547x timers.
These 32-bit timers can capture timer values, trigger external events or internal interrupts, or count external
events.
1.5.1.13.1 Timer Inputs (TIN[3:0])
TINn can be programmed as clocks that cause events in the counter and prescalers. They can also cause
captures on the rising edge, falling edge, or both edges.
1.5.1.13.2 Timer Outputs (TOUT[3:0])
The programmable timer outputs, TOUTn, pulse or toggle on various timer events.
1.5.1.14 Debug Support Signals
The MCF547x complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are multiplexed with
background debug pins. Except for TCK, these signals are selected by the value of MTMOD0. If MTMOD0
is high, JTAG signals are chosen; if it is low, debug module signals are chosen. MTMOD0 should be
changed only while RSTI is asserted.
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