參數(shù)資料
型號(hào): MCF54454VR266
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA360
封裝: 23 X 23 MM, ROHS COMPLIANT, TEPBGA-360
文件頁(yè)數(shù): 41/48頁(yè)
文件大小: 945K
代理商: MCF54454VR266
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 6
Revision History
Freescale Semiconductor
46
9
Revision History
Table 34 summarizes revisions to this document.
Table 34. Revision History
Rev. No.
Date
Summary of Changes
0
Sept 17, 2007 Initial public release.
1
Feb 15, 2008 Corrected VSS pin locations in MCF5445x signal information and muxing table for the 360 TEPBGA
package: changed “...M9, M16, M17...” to “...M9–M14, M16...”
Updated FlexBus read and write timing diagrams and added two notes before them.
Added power consumption section.
2
May 1, 2008 In Family Configurations table, added PCI as feature on 256-pin devices. On these devices the
PCI_AD bus is limited to 24-bits.
In Absolute Maximum Ratings table, changed RTCVDD specification from “-0.3 to +4.0” to “-0.5 to
+2.0”.
Changed RTCVDD specification from 3.0–3.6 to 1.35–1.65.
added footnote to this spec: “Worst-case tristate leakage current with only one I/O pin high. Since
all I/Os share power when high, the leakage current is distributed among them. With all I/Os high,
this spec reduces to ±2
μA min/max.“
3
Dec 1, 2008 Changed “360PBGA” heading to “360 TEPBGA” in Table 6.
Changed the following specs in Table 13:
Minimum frequency of operation from — to 60MHz
Maximum clock period from — to 16.67 ns
4
Apr 12, 2009 Rescinded previous errata, the 256-pin devices do not contain the PCI bus controller:
In Table 4, in PCI_ADn signal section, added a separate row for each package, with PCI_ADn
signals shown as — for 256-pin devices.
In Figure 5, changed the PCI_ADn pins to their alternative function, FB_An.
5
Apr 27, 2009 In Table 2 changed MCF54450VM180 to MCF54450CVM180 and changed it’s temperature entry
from “0
° to +70° C” to “–40° to +85° C”
6
Oct 15, 2009 In Table 8 changed Input Leakage Current (Iin) from ±1.0 to ±2.5μA
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