參數(shù)資料
型號(hào)： MCF54454VR266
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA360
封裝： 23 X 23 MM, ROHS COMPLIANT, TEPBGA-360
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 945K
代理商： MCF54454VR266
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
22
5.6
Reset Timing Specifications
Table 11 lists specifications for the reset timing parameters shown in Figure 8.
12
Crystal capacitive load
CL
See crystal spec
13
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
—2
× (C
L -
CS_XTAL -
CS_EXTAL -
CS_PCB)
6
pF
14
Frequency un-LOCK Range
fUL
-4.0
4.0
% fsys
15
Frequency LOCK Range
fLCK
-2.0
2.0
% fsys
17
CLKOUT Period Jitter, 3, 4, 7 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Cjitter
—
10
TBD
% FB_CLK
1 The minimum system frequency is the minimum input clock divided by the maximum low-power divider (16 MHz
÷ 32,768).
When the PLL is enabled, the minimum system frequency (fsys) is 150 MHz.
2
This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock
reference only.
3
Proper PC board layout procedures must be followed to achieve specifications.
4
This parameter is guaranteed by design rather than 100% tested.
5
This specification is the PLL lock time only and does not include oscillator start-up time.
6
CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL.
7
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval.
Table 11. Reset and Configuration Override Timing
Num
Characteristic
Min
Max
Unit
R11
1 RESET and Configuration Override data lines are synchronized internally. Setup and hold times must be met only if
recognition on a particular clock is required.
RESET valid to CLKIN (setup)
9
—
ns
R2
CLKIN to RESET invalid (hold)
1.5
—
ns
R3
RESET valid time2
2 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously
to the system. Thus, RESET must be held a minimum of 100 ns.
5
—
CLKIN cycles
R4
CLKIN to RSTOUT valid
—
10
ns
R5
RSTOUT valid to Configuration Override inputs valid
0
—
ns
R6
Configuration Override inputs valid to RSTOUT invalid (setup)
20
—
CLKIN cycles
R7
Configuration Override inputs invalid after RSTOUT invalid (hold)
0
—
ns
R8
RSTOUT invalid to Configuration Override inputs High Impedance
—
1
CLKIN cycles
Table 10. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
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參數(shù)描述
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