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參數(shù)資料
| 型號： | MCF54454VR266 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA360 |
| 封裝： | 23 X 23 MM, ROHS COMPLIANT, TEPBGA-360 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 945K |
| 代理商： | MCF54454VR266 |
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Electrical Characteristics
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 6
Freescale Semiconductor
33
Figure 18. I2C Input/Output Timings
5.13
Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
5.13.1
Receive Signal Timing Specifications
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
I61
Clock high time
10
—
tSYS
I71
Data setup time
2
—
tSYS
I81
Start condition setup time (for repeated start condition only)
20
—
tSYS
I91
Stop condition setup time
10
—
tSYS
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 19. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR. However, the numbers
given in Table 19 are minimum values.
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
3 Specified at a nominal 50-pF load.
Table 20. Receive Signal Timing
Num
Characteristic
MII Mode
RMII Mode
Unit
Min
Max
Min
Max
—
RXCLK frequency
—
25
—
50
MHz
E1
RXD[n:0], RXDV, RXER to RXCLK setup1
1 In MII mode, n = 3; In RMII mode, n = 1
5—4—
ns
E2
RXCLK to RXD[n:0], RXDV, RXER hold1
5—2—
ns
E3
RXCLK pulse width high
35%
65%
35%
65%
RXCLK period
E4
RXCLK pulse width low
35%
65%
35%
65%
RXCLK period
Table 19. I2C Output Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Units
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF54455 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor |
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| MCF54455_0812 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF5445x ColdFire?? Microprocessor Data Sheet |
| MCF54455_09 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF5445x ColdFire?? Microprocessor Data Sheet |
| MCF54455ACVR200 | 制造商:Freescale Semiconductor 功能描述:MCF5445X RISC 32-BIT 200MHZ 1.8V/2.5V/3.3V 360-PIN TEBGA TRA - Trays |
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