參數(shù)資料
型號(hào)： MCF54454VR266
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA360
封裝： 23 X 23 MM, ROHS COMPLIANT, TEPBGA-360
文件頁(yè)數(shù)： 13/48頁(yè)
文件大?。?/td> 945K
代理商： MCF54454VR266
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
20
5.5
ClockTiming Specifications
The clock module configures the device for one of several clocking methods. Clocking modes include internal phase-locked
loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier.
The PLL can also be disabled, and an external oscillator can directly clock the device.
The specifications in Table 9 are for the CLKIN input pin (EXTAL input driven by an external clock reference). The duty cycle
specification is based on an acceptable tolerance for the PLL, which yields 50% duty-cycle internal clocks to all on-chip
peripherals. The MCF5445x devices use the input clock signal as its synchronous bus clock for PCI. A poor duty cycle on the
input clock, may affect the overall timing margin to external devices. If negative edge logic is used to interface to PCI, providing
a 50% duty-cycle input clock aids in simplifying overall system design.
Weak Internal Pull Up Device Current, tested at VIL Max.
3
IAPU
–10
–130
μA
Input Capacitance 4
All input-only pins
All input/output (three-state) pins
Cin
—
7
pF
Load Capacitance
Low drive strength
High drive strength
CL
25
50
pF
DC Injection Current 3, 5, 6, 7
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
IIC
-1.0
-10
1.0
10
mA
1 IV
DD and PVDD should be at the same voltage. PVDD should have a filtered input. Please see the PLL section of this
specification for an example circuit. There are three PVDD inputs, one for each PLL. A filter circuit should used on each
PVDD input.
2 Worst-case tristate leakage current with only one I/O pin high. Since all I/Os share power when high, the leakage current
is distributed among them. With all I/Os high, this spec reduces to ±2
μA min/max.
3 Refer to the MCF54455 Reference Manual signals description chapter for pins having weak internal pull-up devices.
4 This parameter is characterized before qualification rather than 100% tested.
5 All functional non-supply pins are internally clamped to V
SS and their respective VDD.
6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
7 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure the external VDD load shunts current greater
than the maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up,
the system clock is not present during the power-up sequence until the PLL has attained lock.
Table 9. Input Clock Timing Requirements
Item
Specification
Min
Max
Unit
C1
Cycle time
15
40
ns
Table 8. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Units
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCF54455 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor
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MCF54455_0812 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF5445x ColdFire?? Microprocessor Data Sheet
MCF54455_09 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF5445x ColdFire?? Microprocessor Data Sheet
MCF54455ACVR200 制造商:Freescale Semiconductor 功能描述:MCF5445X RISC 32-BIT 200MHZ 1.8V/2.5V/3.3V 360-PIN TEBGA TRA - Trays
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