參數(shù)資料
型號(hào)： MC92602ZTA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196
文件頁數(shù)： 41/102頁
文件大小： 1581K
代理商： MC92602ZTA
MOTOROLA
Chapter 4. Rate Adaption of Packet Data Streams
4-1
Chapter 4
Rate Adaption of Packet Data Streams
This chapter describes how the MC92602 performs rate adaption in applications where the
device is used to transmit and receive PCS, PMA, type 1000BASE-X packet streams. This
chapter consists of the following sections:
When the MC92602 is being operated in reference clock mode, as described in
account for frequency offset between the transmitter and receiver. In backplane
applications, rate adaption is accommodated by adding K28.5 idle code groups (characters)
to, or deleting K28.5 idle code groups from, the data stream to match the incoming data rate
to the receiver data rate, as defined by its reference clock frequency. This indiscriminate
addition or deletion of K28.5 idle characters from an 802.3 packet stream would interfere
with proper system operation.
NOTE
Rate adaption is necessary only if the MC92602 is being
operated in the reference clock mode (RCCE = low).
The MC92602 compatibility mode, COMPAT, allows for rate adaption using methods
compatible with 802.3 packet streams and does not interfere with proper system operation.
The following are the features of compatibility mode:
Context sensitive rate adaption during receipt of configuration, idle, and data code
groups.
Tolerates up to +100 ppm frequency offset.
Supports Jumbo frame lengths of up to 16 Kbytes.
Supports frame bursting.
Internal or external 8B/10B encoding/decoding may be used.
Compatible with specification of media access control function.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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