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| 型號(hào)： | MC92602ZTA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196 |
| 文件頁數(shù)： | 38/102頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | MC92602ZTA |
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3-12
MC92602 SerDes Reference Manual
MOTOROLA
Functional Description
The priority column in the tables show the error that is reported if multiple errors occur at
the same time. The lower-priority numbered errors are reported first.
3.3.7
Receiver Interface Clock Timing Modes
The receiver interface is double data rate, source synchronous. Each of the receiver’s six
output signals are timed, relative to the rising and falling edges of the receiver interface
clock output, RECV_x_CLK. The receiver interface clock frequency may be selected
between its own recovered clock frequency, receiver A’s recovered clock frequency, or the
frequency of the reference clock input REF_CLK.
The recovered clock enable signal, RCCE, determines if the receiver interface is timed to
the recovered clock or to the local reference clock. Asserting RCCE enables timing relative
to the recovered clock, and set low enables timing relative to the reference clock. When
RCCE is asserted high, the signal, RECV_REF_A, is used to select the recovered clock to
be used. If RECV_REF_A is asserted, then channel A’s recovered clock is used for all four
channels. If it is low, then each channel uses its own recovered clock.
The receiver interface clock signals, RECV_x_CLK, will always be present when the PLL
is in lock. This is true even if there is no signal present on the serial inputs or if the receiver
has not achieved alignment or byte sync. The frequency of the receiver clock will be the
local reference clock. The clock signals, however, are not present during power up or when
the MC92602 is in reset mode and the PLL is not locked.
3.3.7.1
Recovered Clock Timing Mode
With RCCE asserted, the recovered clock signal, RECV_x_CLK, is generated by the
receiver and, on average, runs at the reference clock frequency of the transmitter at the other
end of the link. The recovered clock is not generated by a clock recovery PLL, but is
generated by the receiver bit-accumulation and byte-alignment logic.
In order to track a transmitter frequency that is offset from the receiver’s reference clock
frequency, the duty cycle and period of the recovered clock is modulated. The MC92602 is
designed to tolerate up to a 250-ppm of frequency offset between transmitter and receiver.
Table 3-7. Receiver Interface Error Codes (Ten-Bit Interface, TBIE = High)
E0
E1
Priority
Description
Low
4
Normal operation, non-idle character received.
Low
High
3
Normal operation, idle (K28.5) character received.
High
Low
1
Overrun/underrun: The receiver interface synchronization logic detected and
overrun/underrun condition. Data may be dropped or repeated.
High
2
Not byte/word sync: The receiver is in start-up or has lost byte or word
alignment and is searching for alignment.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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