參數(shù)資料
型號(hào)： MC92602ZTA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196
文件頁數(shù)： 50/102頁
文件大小： 1581K
代理商： MC92602ZTA
MOTOROLA
Chapter 5. System Design Considerations
5-3
Configuration and Control Signals
5.4
Configuration and Control Signals
The MC92602 has many configuration and control signals that are asynchronous to all
inputs clocks. Most of the signals affect the internal configuration state and must be set at
power up. If their state is changed after power up, some require that the chip be reset by
setting RESET low and then releasing high. While other configuration signals are meant to
be changed during normal operation and do not require chip reset. However, these signals
may still affect device operation. Table 5-3 lists all of the MC92602 asynchronous
configuration and control signals and describes the effect of changing their state after power
up.
Table 5-3. Asynchronous Configuration and Control Signals
Signal Name
Description
Effect of Changed State
XCVR_x_DISABLE
Transceiver disable
Receiver must acquire new bit phase alignment;
byte and word synchronization must be
re-established.
DROP_SYNC
Drop synchronization
Receiver must re-establish byte and word
synchronization.
XMIT_REF_A
Transmitter reference clock A select
Device must be reset
RECV_REF_A
Receiver reference clock A select
Device must be reset
TBIE
Ten-bit interface enable
Device must be reset
HSE
Half-speed enable
Device must be reset
BSYNC
Byte synchronization mode
Device must be reset
ADIE
Add/drop idle enable
Device must be reset
COMPAT
Compatibility mode
Device must be reset
REPE
Repeater mode enable
Must be low and remain low during normal
operation.
RCCE
Recovered clock enable
Device must be reset
WSE
Word synchronization enable
Device must be reset
TST_0, TST_1
Test mode identifiers
Must be low and remain low during normal
operation.
LBE
loopback enable
Receiver must acquire new bit phase alignment;
byte and word synchronization must be
re-established.
LBOE
loopback output enable
Enable/disable transmit links during testing
(LBOE = high), no recovery action necessary.
STNDBY
Puts PLL in standby mode
Receiver must re-establish byte and word
synchronization.
RESET
System reset bar
Device is reset
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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