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參數(shù)資料
| 型號： | MC92602ZTA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196 |
| 文件頁數(shù)： | 31/102頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | MC92602ZTA |
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3-6
MC92602 SerDes Reference Manual
MOTOROLA
Functional Description
The transition tracking loop is tolerant of frequency offset between the transmitter and
receiver. The MC92602 reliably operates with +250 ppm of frequency offset. The transition
tracking loop method is different than the typical PLL clock recovery method. Its receiver
compensates for overrun and underrun due to frequency offset by modulating the
duty-cycle and period of the received byte clock such that it matches the frequency of the
received data (see Section 3.3.7.1, “Recovered Clock Timing Mode,” for more
information).
Recovered data is accumulated into 10-bit characters. The characters are aligned to their
original 10-bit boundaries if a byte alignment mode is enabled.
3.3.3
Byte Alignment
The receiver supports two modes of byte alignment as defined by the BSYNC signal.
Table 3-2 shows the settings to activate each mode.
3.3.3.1
Byte-Aligned
At power up, the receiver starts an alignment procedure, searching for the 10-bit pattern
defined by the 8B/10B idle code. Synchronization logic checks for the distinct idle
sequence, ‘0011111010’ and ‘1100000101’ (ordered bit 0 to bit 9), characteristic of the
K28.5 idle pattern. The search is done on the 10-bit data in the receiver and is, therefore,
independent of the TBIE input. Alignment requires a minimum of four, error-free, received
idle characters to ensure proper alignment and lock. Non-idle characters may be
interspersed with the idle characters. The disparity of the idle characters is not important to
alignment and can be positive, negative, or any combination.
The receiver begins to forward received characters once locked on an alignment. However,
if Word Synchronization Enable is asserted, WSE = high, received characters are not
forwarded to the receiver interface until the first valid non-idle character is received.
Alignment remains locked until any one of three events occur that indicate loss of
alignment:
Alignment is lost when a misaligned idle sequence is detected. A misaligned idle
sequence is defined as four idle characters with an alignment different than the
current alignment. Non-idle characters may be dispersed between the four
misaligned idles, however, a properly aligned idle character breaks the sequence.
Although alignment is lost by this condition, the receiver automatically changes
alignment to the newly detected alignment. However, status out will be reported as
Table 3-2. Byte Synchronization Modes
Byte Alignment Mode
BSYNC
Byte aligned
High
Non-aligned
Low
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For More Information On This Product,
Go to: www.freescale.com
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| MC92603VM | 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604VM | 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:25 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| MC92610 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES |
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