- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45309 > MC8DE08GQAPR-MWA FLASH MEMORY DRIVE CONTROLLER, PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MC8DE08GQAPR-MWA |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA |
| 封裝： | FBGA |
| 文件頁(yè)數(shù)： | 9/65頁(yè) |
| 文件大小： | 799K |
| 代理商： | MC8DE08GQAPR-MWA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)
NAND Flash-based Solid State Disk
17
Sep. 27. 2006
Figure 1 defines the relationships between the interface signals for register transfers. Peripherals reporting support for PIO mode 3 or
4 shall power-up in a PIO mode 0,1, or 2.
For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 1
defines the minimum value that shall be placed in word 68.
Both hosts and devices shall support IORDY when PIO mode 3 or 4 are the currently selected mode of operation.
DIOR-/DIOW-
WRITE DD(7:0)
READ DD(7:0)
IORDY
t1
ADDR valid
t2
(See note 1)
(See note 2)
(See note 3,3-2)
IORDY
(See note 3,3-1)
IORDY
(See note 3,3-3)
t9
t0
t3
t4
t5
t6
t6Z
tA
tC
tRD
tB
tC
NOTE:
1. Device address consists of signals CS0-, CS1- and DA(2:0)
2. Data consists of DD(7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made
by the host after tA from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases:
3-1. Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2. Device negates IORDY before tA, but causes IORDY to be asserted before tA.
IORDY is released prior to negation and may be asserted for no more than 5ns before release: no wait generated.
3-3. Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5ns before release: wait generated.
The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on
DD(7:0) for tRD before asserting IORDY.
4. DMACK- shall remain negated during a register transfer.
Figure 1. Register transfer to/from device.
t2i
4.5.1 Register Transfers
4.5 AC Characteristics
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCC3E0RX180WB0B | 180 MHz, RISC PROCESSOR, CBGA728 |
| MCCF68HC08LK60 | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC150 |
| MCW68HC08LK60 | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC150 |
| MCD214FU | 768 X 560 PIXELS CRT GRPH DSPL CTLR, PQFP160 |
| MCF5102PV20A | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8DE16G5APP-0XA00 | 制造商:Samsung Semiconductor 功能描述: |
| MC8F-1 | 制造商:SPC Multicomp 功能描述:TRANSFORMER VARIABLE 8A |
| MC8F-1 | 制造商:SPC Multicomp 功能描述:TRANSFORMER VARIABLE 8A |
| MC8M | 制造商:G & J HALL 功能描述:STEP DRILL MULTICUT 14-24MM X 2MM |
| MC8MD9P1B10M2RES | 制造商:SPC Multicomp 功能描述:SWITCH DPST OFF-MOM PCB 制造商:SPC Multicomp 功能描述:SWITCH, DPST, OFF-MOM, PCB 制造商:SPC Multicomp 功能描述:SWITCH, DPST, OFF-MOM, PCB; Contact Configuration:DPST; Switch Operation:Off-(On); Contact Voltage AC Nom:20V; IP Rating:(Not Available); Contact Voltage DC Nom:20V; Contact Current Max:400mA; Actuator Style:Round; Switch ;RoHS Compliant: Yes |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。