參數(shù)資料
型號(hào): MC8DE08GQAPR-MWA
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA
封裝: FBGA
文件頁數(shù): 17/65頁
文件大?。?/td> 799K
代理商: MC8DE08GQAPR-MWA
NAND Flash-based Solid State Disk
24
Sep. 27. 2006
The values for the timings for each of the Multiword DMA modes are contained in Table 50.
DMARQ
WRITE
CS0-/CS1-
DD(15:0)
READ
DD(15:0)
Figure 5. Device terminating a Multiword DMA data transfer
DIOR-/DIOW-
DMACK-
t0
tK
tE
tG
tF
tG
tH
(See note)
tN
tL
tD
tJ
tZ
NOTE:
To terminate the data burst, the Host shall negate DMARQ within the tL of the assertion of the current DIOR- or DIOW- pulse. The last data word for the
burst shall then be transferred by the negation of the current DIOR- or DIOW- pulse. If all data for the command has not been transferred, the Host shall
reassert DMARQ again at any later time to resume the DMA operation.
4.5.3.3 Device terminating a Multiword DMA data burst
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