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參數(shù)資料
| 型號(hào)： | MC8DE08GQAPR-MWA |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA |
| 封裝： | FBGA |
| 文件頁(yè)數(shù)： | 39/65頁(yè) |
| 文件大小： | 799K |
| 代理商： | MC8DE08GQAPR-MWA |
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NAND Flash-based Solid State Disk
44
Sep. 27. 2006
5.9.1 Address
CS1
CS0
DA2
DA1
DA0
NA
A
N
A=asserted, N=negated
NOTE:
Some hosts set these bits to one. Devices shall ignore these bits.
Obsolete:These bits are obsolete.
#:The content of these bits is command dependent
DEV: Device select. Cleared to zero selects Device 0. Set to one selects Device1.
7
6
5
432
1
0
Obsolete
#
Obsolete
DEV
#
5.9.2 Direction
This register is read/write.
5.9.3 Access Restrictions
This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted.
The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY or DRQ is set to one, the
result is indeterminate.
5.9.4 Effect
The DEV bit becomes effective when this register is written by the host or the signature is set by the device. All other bits in this reg-
ister become a command parameter when the Command register is written.
5.9.5 Functional description
But 4, DEV, in this register selects the device. Other bits in this register are command dependent.
5.9.6 Field / bit description
The content of this register shall take effect when written.
5.9 Device / Head Register
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