參數(shù)資料
型號: MC8DE08GQAPR-MWA
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA
封裝: FBGA
文件頁數(shù): 32/65頁
文件大?。?/td> 799K
代理商: MC8DE08GQAPR-MWA
NAND Flash-based Solid State Disk
38
Sep. 27. 2006
5.3 Command Register
5.3.1 Address
CS1
CS0
DA2
DA1
DA0
NA
A
N
A=asserted, N=negated
This register is write only. If this address is read by the host, the Status register is read.
5.3.3 Access Restrictions
For all commands, this register shall only be written when BSY and DRQ are both cleared to zero and DMACK- is not asserted. If
written when BSY or DRQ is set to one, the results of writing the Command register are indeterminate.
5.3.4 Effect
5.3.5 Functional description
5.3.6 Field/bit description
7
6
5
4
3
2
1
0
Command Code
Command prcessing begins when this register is writte. The content of the Command Blcok registers become parameters of the
command when this register is written. Writing this register clears any pending interrupt condition.
This register contains the command code being sent to the device. Command execution begins immediately after this register is writ-
ten.
5.3.2 Direction
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