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參數(shù)資料
| 型號： | MC80C52XXX-16/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 8/204頁 |
| 文件大小： | 5687K |
| 代理商： | MC80C52XXX-16/883 |
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105
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
15.6.2
ADC Voltage Reference
The ADC reference voltage (V
REF) indicates the conversion range for the ADC. Single ended channels that exceed
V
REF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference. The internal
1.1V reference is generated from the internal bandgap reference (V
BG) through an internal amplifier.
The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is
advised to discard this result.
15.7
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode. This reduces noise induced from
the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle
mode. To make use of this feature, the following procedure should be used:
Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and
the ADC conversion complete interrupt must be enabled.
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been
halted.
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and
execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC
conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will
be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep
command is executed.
Note that the ADC will not automatically be turned off when entering other sleep modes than Idle mode and ADC
Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid
excessive power consumption.
15.8
Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 15-8. An analog source applied to ADCn
is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as
input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resis-
tance (combined resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 k
or less. If such a source
is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will
depend on how long time the source needs to charge the S/H capacitor, which can vary widely. The user is recom-
mended to only use low impedance sources with slowly varying signals, since this minimizes the required charge
transfer to the S/H capacitor.
In order to avoid distortion from unpredictable signal convolution, signal components higher than the Nyquist fre-
quency (f
ADC/2) should not be present. The user is advised to remove high frequency components with a low-pass
filter before applying the signals as inputs to the ADC.
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