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參數(shù)資料
| 型號(hào)： | MC80C52XXX-16/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 185/204頁(yè) |
| 文件大?。?/td> | 5687K |
| 代理商： | MC80C52XXX-16/883 |
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81
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
Figure 12-3. Output Compare Unit, Block Diagram
12.6.1
Compare Match Blocking by TCNT1 Write
All CPU write operations to the TCNT1H/L Register will block any Compare Match that occur in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR1A/B to be initialized to the same value as TCNT1
without triggering an interrupt when the Timer/Counter clock is enabled.
12.6.2
Using the Output Compare Unit
Since writing TCNT1H/L will block all Compare Matches for one timer clock cycle, there are risks involved when
changing TCNT1H/L when using the Output Compare Unit, independently of whether the Timer/Counter is running
or not. If the value written to TCNT1H/L equals the OCR1A/B value, the Compare Match will be missed.
12.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
Timer/Counter Width (TCW1), Input Capture Enable (ICEN1) and CTC Mode (CTC1) bits. See “TCCR1A –
Table 12-3 summarises the different modes of operation.
12.7.1
Normal, 8-bit Mode
In Normal 8-bit mode (see Table 12-3), the counter (TCNT1L) is incrementing until it overruns when it passes its
maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom (0x00). The Overflow Flag (TOV1) is set in
the same timer clock cycle as when TCNT1L becomes zero. The TOV1 Flag in this case behaves like a ninth bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears
the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the
Normal 8-bit mode, a new counter value can be written anytime. The Output Compare Unit can be used to gener-
ate interrupts at some given time.
12.7.2
Clear Timer on Compare Match (CTC) 8-bit Mode
In Clear Timer on Compare or CTC mode, see Table 12-3 on page 81, the OCR1A Register is used to manipulate
the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches the
OCFnx (Int.Req.)
= (8/16-bit Comparator )
OCRnx
DATA BUS
TCNTn
Table 12-3.
Modes of operation
Mode
ICEN1
TCW1
CTC1
Mode of Operation
TOP
Update of OCRx at
TOV Flag Set on
0000
Normal, 8-bit Mode
0xFF
Immediate
MAX (0xFF)
1001
CTC Mode, 8-bit
OCR0A
Immediate
MAX (0xFF)
2
0
1
X
Normal, 16-bit Mode
0xFFFF
Immediate
MAX (0xFFFF)
3
1
0
X
Input Capture Mode, 8-bit
0xFF
Immediate
MAX (0xFF)
4
1
X
Input Capture Mode, 16-bit
0xFFFF
Immediate
MAX (0xFFFF)
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