
21
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
6.4.2
Starting from Power-Down Mode
When waking up from Power-down sleep mode, the supply voltage is assumed to be at a sufficient level and only
the oscillator start-up time is counted to ensure the stable operation of the oscillator. The oscillator start-up time is
counted on the selected main clock, and the start-up time depends on the clock selected. See
Table 6-2 for details.
Notes:
1. The start-up time is measured in main clock oscillator cycles.
2. When using software BOD disable, the wake-up time from sleep mode will be approximately 60s.
6.4.3
Starting from Idle / ADC Noise Reduction / Standby Mode
When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and no oscilla-
tor start-up time is introduced.
6.5
Register Description
6.5.1
CLKMSR – Clock Main Settings Register
Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bits 1:0 – CLKMS[1:0]: Clock Main Select Bits
These bits select the main clock source of the system. The bits can be written at run-time to switch the source of
the main clock. The clock system ensures glitch free switching of the main clock source.
The main clock alternatives are shown in
Table 6-3.
To avoid unintentional switching of main clock source, a protected change sequence must be followed to change
the CLKMS bits, as follows:
1.
Write the signature for change enable of protected I/O register to register CCP
2.
Within four instruction cycles, write the CLKMS bits with the desired value
Table 6-2.
Start-up Time from Power-Down Sleep Mode.
Oscillator start-up time
Total start-up time
6 cycles
Bit
765
432
1
0
–
CLKMS1
CLKMS0
CLKMSR
Read/Write
R
R/W
Initial Value
0
Table 6-3.
Selection of Main Clock
CLKM1
CLKM0
Main Clock Source
0
Calibrated Internal 8 MHzOscillator
0
1
Internal 128 kHz Oscillator (WDT Oscillator)
1
0
External clock
11
Reserved