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ATtiny40 [DATASHEET]
8263B–AVR–01/2013
18.3
Physical Layer of Tiny Programming Interface
The TPI physical layer handles the basic low-level serial communication. The TPI physical layer uses a bi-direc-
tional, half-duplex serial receiver and transmitter. The physical layer includes serial-to-parallel and parallel-to-serial
data conversion, start-of-frame detection, frame error detection, parity error detection, parity generation and colli-
sion detection.
The TPI is accessed via three pins, as follows:
RESET:
Tiny Programming Interface enable input
TPICLK:
Tiny Programming Interface clock input
TPIDATA:
Tiny Programming Interface data input/output
In addition, the V
CC and GND pins must be connected between the external programmer and the device.
18.3.1
Enabling
The following sequence enables the Tiny Programming Interface:
Apply 5V between V
CC and GND
Depending on the method of reset to be used:
– Either: wait t
device and enable the TPI physical layer. The RESET pin must then be kept low for the entire
programming session
– Or: if the RSTDISBL configuration bit has been programmed, apply 12V to the RESET pin. The RESET
pin must be kept at 12V for the entire programming session
Wait t
Keep the TPIDATA pin high for 16 TPICLK cycles
Figure 18-2. Sequence for enabling the Tiny Programming Interface
18.3.2
Disabling
Provided that the NVM enable bit has been cleared, the TPI is automatically disabled if the RESET pin is released
to inactive high state or, alternatively, if V
HV is no longer applied to the RESET pin.
If the NVM enable bit is not cleared a power down is required to exit TPI programming mode.
18.3.3
Frame Format
The TPI physical layer supports a fixed frame format. A frame consists of one character, eight bits in length, and
one start bit, a parity bit and two stop bits. Data is transferred with the least significant bit first.
RESET
t
RST
TPIDATA
TPICLK
16 x TPICLK CYCLES