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ATtiny40 [DATASHEET]
8263B–AVR–01/2013
8.4.2
Code Examples
The following code example shows how to turn off the WDT. The example assumes that interrupts are controlled
(e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Note:
8.5
Register Description
8.5.1
WDTCSR – Watchdog Timer Control and Status Register
Bit 7 – WDIF: Watchdog Timer Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is
cleared by writing a logic one to the flag. When the WDIE is set, the Watchdog Time-out Interrupt is requested.
Bit 6 – WDIE: Watchdog Timer Interrupt Enable
When this bit is written to one, the Watchdog interrupt request is enabled. If WDE is cleared in combination with
this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is requested if time-out in the
Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog
Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hard-
ware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while
using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This
should however not be done within the interrupt service routine itself, as this might compromise the safety-function
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in
r16, RSTFLR
andi
r16, ~(1<<WDRF)
out
RSTFLR, r16
; Write signature for change enable of protected I/O register
ldi
r16, 0xD8
out
CCP, r16
; Within four instruction cycles, turn off WDT
ldi
r16, (0<<WDE)
out
WDTCSR, r16
ret
Bit
765
4321
0
WDIF
WDIE
WDP3
–
WDE
WDP2
WDP1
WDP0
WDTCSR
Read/Write
R/W
R
R/W
Initial Value
0
X
0