參數(shù)資料
型號: MC74AC00M
廠商: ON SEMICONDUCTOR
元件分類: 門電路
英文描述: AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: EIAJ, PLASTIC, 14 PIN
文件頁數(shù): 5/45頁
文件大?。?/td> 434K
代理商: MC74AC00M
http://onsemi.com
17
8
7
6
5
4
3
2
1
0
-60 -40 -20
0
20
40
60
80
100 120
VCC = 5 V
TEMPERATURE (°C)
MAXIMUM
MINIMUM
TYPICAL
Figure 1–11b. tPHL, A to B, All Paths
With voltage and process effects added (Figure 1–11e),
the full range of the specification can be seen. For reference,
the data sheet values are shown on the graph.
1.1
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
0.92
0.9
5.5
5
4.5
VOLTS
Figure 1–11c. Voltage Effects on Delay Times
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
MIN
TYP
MAX
PROCESS WINDOW
Figure 1–11d. FACT Process Effects on Delay Times
8
7
6
5
4
3
2
1
0
-55 -35 -15
5
25
45
65
85
105 125
TEMPERATURE (°C)
MAXIMUM
ROOM TEMP
COMMERCIAL
TYPICAL
MINIMUM
COMMERCIAL
PROP
AGA
TION
DELA
Y(ns)
Figure 1–11e. tPHL, A to B, with Voltage
and Process Variation
This linear behavior with temperature and voltage is
typical of CMOS. Although the graphs are drawn for a
specific device, other part types have very similar graphical
representations.
Therefore,
for
performance-critical
applications, where not all variables need to be taken into
account at once, the user can narrow the specifications. For
example, all parts in a critically timed subcircuit are together
on a board, so it may be assumed the devices are at the same
supply and temperature.
The same reasoning can be applied to setup and hold
times. Consider the ‘AC74. The setup time is 3 ns while the
hold time is 0 ns. Theoretically, if these numbers were
violated, the device would malfunction; however, in
actuality, the device probably will not malfunction. Looking
at the typical setup and hold times gives a better
understanding of the device operation.
At 25
°C and 5 V, the setup time is 1.5 ns while the hold
time is –1.5 ns. They are the same; a positive setup time
means the control signal to be valid before the clock edge,
a positive hold time indicates the control signal will be held
valid after the clock edge for the specified time, and a
negative hold time means the control signal can transition
before the clock edge. FACT devices were designed to be as
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