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參數(shù)資料
| 型號： | MC74AC00M |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 門電路 |
| 英文描述： | AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | EIAJ, PLASTIC, 14 PIN |
| 文件頁數(shù)： | 43/45頁 |
| 文件大?。?/td> | 434K |
| 代理商： | MC74AC00M |
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11
The example below describes typical values for a
74XX138, 3-to-8 line decoder.
FACT =
6.0 ns @ CL = 50 pF
ALS
= 12.0 ns @ CL = 50 pF
LS
= 22.0 ns @ CL = 15 pF
HC
= 17.5 ns @ CL = 50 pF
AC performance specifications are guaranteed at 5 V
±
0.5 V and 3.3 V
± 0.3 V. For worst case design at 2 V VCC
on all device types, the formula below can be used to
determine AC performance.
AC performance at 2 V VCC = 1.9 × AC specification
at 3.3 V.
Multiple Output Switching
Propagation delay is affected by the number of outputs
switching simultaneously. Typically, devices with more than
one output will follow the rule: for each output switching,
derate the databook specification by 250 ps. This effect
typically is not significant on an octal device unless more
than four outputs are switching simultaneously. This
derating is valid for the entire temperature range and 5 V
±
10% VCC.
Noise Immunity
The noise immunity of a logic family is also an important
equipment cost factor in terms of decoupling components,
power supply dynamic resistance and regulation as well as
layout rules for PC boards and signal cables.
The comparisons shown describe the difference between
the input threshold of a device and the output voltage,
VIL – VOL / VIH – VOH at 4.5 V VCC.
FACT = 1.25/1.25 V
ALS
= 0.4/0.7 V
LS
= 0.3/0.7 V @ 4.75 V VCC
HC
= 0.8/1.25 V
Output Characteristics
All FACT outputs are buffered to ensure consistent output
voltage and current specifications across the family. Both
‘AC and ‘ACT device types have the same output structures.
Two clamp diodes are internally connected to the output pin
to suppress voltage overshoot and undershoot in noisy
system applications which can result from impedance
mismatching. The balanced output design allows for
controlled edge rates and equal rise and fall times.
All devices (‘AC or ‘ACT) are guaranteed to source and
sink 24 mA. Commercial devices, 74AC/ACTXXX, are
capable of driving 50 ohm transmission lines.
IOL/IOH Characteristics
FACT = 24/–24 mA
ALS
= 24/–15 mA
LS
= 8/–0.4 mA @ 4.75 V VCC
HC
= 4/–4 mA
Dynamic Output Drive
Traditionally, in order to predict what incident wave
voltages would occur in a system, the designer was required
to do an output analysis using a Bergeron diagram. Not only
is this a long and time consuming operation, but the designer
needed to depend upon the accuracy and reliability of the
manufacturer-supplied
‘typical’
output
I/V
curve.
Additionally, there was no way to guarantee that any
supplied device would meet these ‘typical’ performance
values across the operating voltage and temperature limits.
Fortunately for the system designers, ON Semiconductor
has taken the necessary steps to guarantee incident wave
switching on transmission lines with impedances as low as
50 ohms for the commercial temperature range.
Figure 1–2 shows a Bergeron diagram for switching both
HIGH-to-LOW and LOW-to-HIGH. On the right side of the
graph ( Iout > 0), are the VOH and IIH curves for FACT logic
while on the left side (Iout < 0), are the curves for VOL and
IIL. Although we will only discuss here the LOW-to-HIGH
transition, the information presented may be applied to a
HIGH-to-LOW transition.
7
6
5
4
3
2
1
0
-1
-2
-0.2
-0.1
00.1
0.2
VOL/IOL
VIN/IIN
LINE 2
SLOPE = 50
VOH/IOH
LOW toHIGH
CURRENT (A)
VOL
TS
(V)
HIGHtoLOW
Figure 1–2. Gate Driving 50 Ohm Line
Reflection Diagram
LINE 1
SLOPE =
50
Begin analysis at the VOL (quiescent) point. This is the
intersection of the VOL/IOL curve for the output and the
VIN/IIN curve for the input. For CMOS inputs and outputs,
this point will be approximately 100 mV. Then draw a 50
ohm load line from this intersection to the VOH/IOH curve as
shown by Line 1. This intersection is the voltage that the
incident wave will have. Here it occurs at approximately
3.95 V. Then draw a line with a slope of –50 ohms from this
first intersection point to the VIN/IIN curve as shown by Line
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| MC74AC04MR1 | AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| MC74AC05MR2 | AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| MC74ACT05DT | ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| MC74AC109N | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74AC00MEL | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00MELG | 功能描述:邏輯門 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00ML1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00MR1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00N | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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