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參數(shù)資料
| 型號： | MC74AC00M |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 門電路 |
| 英文描述： | AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | EIAJ, PLASTIC, 14 PIN |
| 文件頁數(shù)： | 3/45頁 |
| 文件大?。?/td> | 434K |
| 代理商： | MC74AC00M |
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15
Section 2 – Circuit Characteristics
Power Dissipation
One advantage to using CMOS logic is its extremely low
power consumption. During quiescent conditions, FACT
will consume several orders of magnitude less current than
its bipolar counterparts. But DC power consumption is not
the whole picture. Any circuit will have AC power
consumption, whether it is built with CMOS or bipolar
technologies.
Power consumption of a circuit can be calculated using
the formula:
PD = [(CL + CPD) VCC VS f] + [IQ VCC]
where
PD
= power dissipation (W)
CL
= load capacitance (Farad)
CPD
= device power capacitance (Farad)
VCC
= power supply (Volt)
VS
= output voltage swing (Volt)
f
= frequency of operation (Hz)
IQ
= quiescent current (Amp)
Power consumption for FACT is dependent on the supply
voltage, frequency of operation, internal capacitance and
load. VS will be VCC and IQ can be considered negligible for
CMOS. Therefore, the simplified formula for CMOS is:
PD = (CL + CPD) VCC2 f
CPD values for CMOS devices are calculated by
measuring the power consumption of a device at two
different frequencies. CPD is calculated in the following
manner:
1. The power supply voltage is set to VCC = 5 Vdc.
2. Signal inputs are set up so that as many outputs as
possible are switching, giving a worst-case situation
per JEDEC CPD conditions (see Section 3).
3. The power supply current is measured and recorded
at input frequencies of 200 kHz and 1 MHz.
4. The power dissipation capacitance is calculated by
solving the two simultaneous equations
P1 = (CPD VCC2 f1) + (ICC VCC)
P2 = (CPD VCC2 f2) + (ICC VCC)
giving
CPD = (P1 – P2)/VCC2(f1 – f2)
or
CPD = (I1 – I2)/VCC(f1 – f2)
where
I1 = supply current at f1 = 200 kHz.
I2 = supply current at f2 = 1 MHz.
On FACT device data sheets, CPD is a typical value and is
given either for the package or for the individual device
function, if there is more than one (i.e., gates, flip-flops,
etc.), within the package.
SET
Q
CLK
D
MC74AC74
CLR
SET
Q
CLK
D
MC74AC74
CLR
SET
Q
CLK
D
MC74AC74
CLR
SET
Q
CLK
D
MC74AC74
E1
E2
E3
A0
A1
A2
O1
O2
O3
O4
O5
O6
O7O8
INPUT
MC74AC04 LOAD DEVICES
MC74AC138
VCC
CLR
Figure 1–9. Power Demonstration Circuit Schematic
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| MC74ACT05DT | ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| MC74AC109N | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC74AC00MEL | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00MELG | 功能描述:邏輯門 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00ML1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00MR1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00N | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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