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參數(shù)資料
| 型號： | MC74AC00M |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 門電路 |
| 英文描述： | AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | EIAJ, PLASTIC, 14 PIN |
| 文件頁數(shù)： | 20/45頁 |
| 文件大?。?/td> | 434K |
| 代理商： | MC74AC00M |
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that CMOS inputs are always driven as close as possible to
the rail.
Figure 1–37. Crystal Oscillator Circuit Implemented
with FACT ‘AC00
Line Driving
With the available high-speed logic families, designers
can reach new heights in system performance. Yet, these
faster devices require a closer look at transmission line
effects.
Although all circuit conductors have transmission line
properties, these characteristics become significant when
the edge rates of the drivers are equal to or less than three
times the propagation delay of the line. Significant
transmission line properties may be exhibited in an example
where devices have edge rates of 3 ns and lines of 8 inches
or greater, assuming propagation delays of 1.7 ns/ft for an
unloaded printed circuit trace.
Of the many properties of transmission lines, two are of
major interest to the system designer: Zoe, the effective
equivalent impedance of the line, and tpde, the effective
propagation delay down the line. It should be noted that the
intrinsic values of line impedance and propagation delay, Zo
and tpd, are geometry-dependent. Once the intrinsic values
are known, the effects of gate loading can be calculated. The
loaded values for Zoe and tpde can be calculated with:
Zoe +
Zo
1
) C
t Cl
t
pde +
t
pd
1
) C
t Cl
where CI = intrinsic line capacitance and Ct = additional
capacitance due to gate loading.
The formulas indicate that the loading of lines decreases
the effective impedance of the line and increases the
propagation delay. Lines that have a propagation delay
greater than one third the rise time of the signal driver should
be evaluated for transmission line effects. When performing
transmission line analysis on a bus, only the longest, most
heavily loaded and the shortest, least loaded lines need to be
analyzed. All lines in a bus should be terminated equally; if
one line requires termination, all lines in the bus should be
terminated. This will ensure similar signals on all of the
lines.
There are several termination schemes which may be
used. Included are series, parallel, AC parallel and Thevenin
terminations. AC parallel and series terminations are the
most useful for low power applications since they do not
consume any DC power. Parallel and Thevenin terminations
experience high DC power consumption.
Termination Schemes
a: No Termination
b: Series Termination
c: Parallel Termination
Figure 1–38. Termination Schemes
d: AC Parallel Termination
e: Thevenin Termination
Series Terminations
Series terminations are most useful in high-speed
applications where most of the loads are at the far end of the
line. Loads that are between the driver and the end of the line
will receive a two-step waveform. The first wave will be the
incident wave. The amplitude is dependent upon the output
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74AC00MEL | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00MELG | 功能描述:邏輯門 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00ML1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00MR1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00N | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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